1 /*
2 * Universal Interface for Intel High Definition Audio Codec
3 *
4 * HD audio interface patch for Silicon Labs 3054/5 modem codec
5 *
6 * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
7 * Takashi Iwai <tiwai@suse.de>
8 *
9 *
10 * This driver is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This driver is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24
25 #include <sound/driver.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/slab.h>
29 #include <linux/pci.h>
30 #include <sound/core.h>
31 #include "hda_codec.h"
32 #include "hda_local.h"
33
34
35 /* si3054 verbs */
36 #define SI3054_VERB_READ_NODE 0x900
37 #define SI3054_VERB_WRITE_NODE 0x100
38
39 /* si3054 nodes (registers) */
40 #define SI3054_EXTENDED_MID 2
41 #define SI3054_LINE_RATE 3
42 #define SI3054_LINE_LEVEL 4
43 #define SI3054_GPIO_CFG 5
44 #define SI3054_GPIO_POLARITY 6
45 #define SI3054_GPIO_STICKY 7
46 #define SI3054_GPIO_WAKEUP 8
47 #define SI3054_GPIO_STATUS 9
48 #define SI3054_GPIO_CONTROL 10
49 #define SI3054_MISC_AFE 11
50 #define SI3054_CHIPID 12
51 #define SI3054_LINE_CFG1 13
52 #define SI3054_LINE_STATUS 14
53 #define SI3054_DC_TERMINATION 15
54 #define SI3054_LINE_CONFIG 16
55 #define SI3054_CALLPROG_ATT 17
56 #define SI3054_SQ_CONTROL 18
57 #define SI3054_MISC_CONTROL 19
58 #define SI3054_RING_CTRL1 20
59 #define SI3054_RING_CTRL2 21
60
61 /* extended MID */
62 #define SI3054_MEI_READY 0xf
63
64 /* line level */
65 #define SI3054_ATAG_MASK 0x00f0
66 #define SI3054_DTAG_MASK 0xf000
67
68 /* GPIO bits */
69 #define SI3054_GPIO_OH 0x0001
70 #define SI3054_GPIO_CID 0x0002
71
72 /* chipid and revisions */
73 #define SI3054_CHIPID_CODEC_REV_MASK 0x000f
74 #define SI3054_CHIPID_DAA_REV_MASK 0x00f0
75 #define SI3054_CHIPID_INTERNATIONAL 0x0100
76 #define SI3054_CHIPID_DAA_ID 0x0f00
77 #define SI3054_CHIPID_CODEC_ID (1<<12)
78
79 /* si3054 codec registers (nodes) access macros */
80 #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
81 #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
82
83
84 struct si3054_spec {
85 unsigned international;
86 struct hda_pcm pcm;
87 };
88
89
90 /*
91 * Modem mixer
92 */
93
94 #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
95 #define PRIVATE_REG(val) ((val>>16)&0xffff)
96 #define PRIVATE_MASK(val) (val&0xffff)
97
98 static int si3054_switch_info(struct snd_kcontrol *kcontrol,
99 struct snd_ctl_elem_info *uinfo)
100 {
101 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
102 uinfo->count = 1;
103 uinfo->value.integer.min = 0;
104 uinfo->value.integer.max = 1;
105 return 0;
106 }
107
108 static int si3054_switch_get(struct snd_kcontrol *kcontrol,
109 struct snd_ctl_elem_value *uvalue)
110 {
111 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
112 u16 reg = PRIVATE_REG(kcontrol->private_value);
113 u16 mask = PRIVATE_MASK(kcontrol->private_value);
114 uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
115 return 0;
116 }
117
118 static int si3054_switch_put(struct snd_kcontrol *kcontrol,
119 struct snd_ctl_elem_value *uvalue)
120 {
121 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
122 u16 reg = PRIVATE_REG(kcontrol->private_value);
123 u16 mask = PRIVATE_MASK(kcontrol->private_value);
124 if (uvalue->value.integer.value[0])
125 SET_REG(codec, reg, (GET_REG(codec, reg)) | mask);
126 else
127 SET_REG(codec, reg, (GET_REG(codec, reg)) & ~mask);
128 return 0;
129 }
130
131 #define SI3054_KCONTROL(kname,reg,mask) { \
132 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
133 .name = kname, \
134 .info = si3054_switch_info, \
135 .get = si3054_switch_get, \
136 .put = si3054_switch_put, \
137 .private_value = PRIVATE_VALUE(reg,mask), \
138 }
139
140
141 static struct snd_kcontrol_new si3054_modem_mixer[] = {
142 SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
143 SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
144 {}
145 };
146
147 static int si3054_build_controls(struct hda_codec *codec)
148 {
149 return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
150 }
151
152
153 /*
154 * PCM callbacks
155 */
156
157 static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
158 struct hda_codec *codec,
159 unsigned int stream_tag,
160 unsigned int format,
161 struct snd_pcm_substream *substream)
162 {
163 u16 val;
164
165 SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
166 val = GET_REG(codec, SI3054_LINE_LEVEL);
167 val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
168 val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
169 SET_REG(codec, SI3054_LINE_LEVEL, val);
170
171 snd_hda_codec_setup_stream(codec, hinfo->nid,
172 stream_tag, 0, format);
173 return 0;
174 }
175
176 static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
177 struct hda_codec *codec,
178 struct snd_pcm_substream *substream)
179 {
180 static unsigned int rates[] = { 8000, 9600, 16000 };
181 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
182 .count = ARRAY_SIZE(rates),
183 .list = rates,
184 .mask = 0,
185 };
186 substream->runtime->hw.period_bytes_min = 80;
187 return snd_pcm_hw_constraint_list(substream->runtime, 0,
188 SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
189 }
190
191
192 static struct hda_pcm_stream si3054_pcm = {
193 .substreams = 1,
194 .channels_min = 1,
195 .channels_max = 1,
196 .nid = 0x1,
197 .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
198 .formats = SNDRV_PCM_FMTBIT_S16_LE,
199 .maxbps = 16,
200 .ops = {
201 .open = si3054_pcm_open,
202 .prepare = si3054_pcm_prepare,
203 },
204 };
205
206
207 static int si3054_build_pcms(struct hda_codec *codec)
208 {
209 struct si3054_spec *spec = codec->spec;
210 struct hda_pcm *info = &spec->pcm;
211 si3054_pcm.nid = codec->mfg;
212 codec->num_pcms = 1;
213 codec->pcm_info = info;
214 info->name = "Si3054 Modem";
215 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
216 info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm;
217 info->is_modem = 1;
218 return 0;
219 }
220
221
222 /*
223 * Init part
224 */
225
226 static int si3054_init(struct hda_codec *codec)
227 {
228 struct si3054_spec *spec = codec->spec;
229 unsigned wait_count;
230 u16 val;
231
232 snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
233 snd_hda_codec_write(codec, codec->mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
234 SET_REG(codec, SI3054_LINE_RATE, 9600);
235 SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
236 SET_REG(codec, SI3054_EXTENDED_MID, 0);
237
238 wait_count = 10;
239 do {
240 msleep(2);
241 val = GET_REG(codec, SI3054_EXTENDED_MID);
242 } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
243
244 if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
245 snd_printk(KERN_ERR "si3054: cannot initialize. EXT MID = %04x\n", val);
246 return -EACCES;
247 }
248
249 SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
250 SET_REG(codec, SI3054_GPIO_CFG, 0x0);
251 SET_REG(codec, SI3054_MISC_AFE, 0);
252 SET_REG(codec, SI3054_LINE_CFG1,0x200);
253
254 if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
255 snd_printd("Link Frame Detect(FDT) is not ready (line status: %04x)\n",
256 GET_REG(codec,SI3054_LINE_STATUS));
257 }
258
259 spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
260
261 return 0;
262 }
263
264 static void si3054_free(struct hda_codec *codec)
265 {
266 kfree(codec->spec);
267 }
268
269
270 /*
271 */
272
273 static struct hda_codec_ops si3054_patch_ops = {
274 .build_controls = si3054_build_controls,
275 .build_pcms = si3054_build_pcms,
276 .init = si3054_init,
277 .free = si3054_free,
278 #ifdef CONFIG_PM
279 //.suspend = si3054_suspend,
280 .resume = si3054_init,
281 #endif
282 };
283
284 static int patch_si3054(struct hda_codec *codec)
285 {
286 struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
287 if (spec == NULL)
288 return -ENOMEM;
289 codec->spec = spec;
290 codec->patch_ops = si3054_patch_ops;
291 return 0;
292 }
293
294 /*
295 * patch entries
296 */
297 struct hda_codec_preset snd_hda_preset_si3054[] = {
298 { .id = 0x163c3055, .name = "Si3054", .patch = patch_si3054 },
299 { .id = 0x163c3155, .name = "Si3054", .patch = patch_si3054 },
300 { .id = 0x11c13026, .name = "Si3054", .patch = patch_si3054 },
301 {}
302 };
303
304
This page was automatically generated by the
LXR engine.
Visit the LXR main site for more
information.