1 /*
2 * 3COM "EtherLink MC/32" Descriptions
3 */
4
5 /*
6 * Registers
7 */
8
9 #define HOST_CMD 0
10 #define HOST_CMD_START_RX (1<<3)
11 #define HOST_CMD_SUSPND_RX (3<<3)
12 #define HOST_CMD_RESTRT_RX (5<<3)
13
14 #define HOST_CMD_SUSPND_TX 3
15 #define HOST_CMD_RESTRT_TX 5
16
17
18 #define HOST_STATUS 2
19 #define HOST_STATUS_CRR (1<<6)
20 #define HOST_STATUS_CWR (1<<5)
21
22
23 #define HOST_CTRL 6
24 #define HOST_CTRL_ATTN (1<<7)
25 #define HOST_CTRL_RESET (1<<6)
26 #define HOST_CTRL_INTE (1<<2)
27
28 #define HOST_RAMPAGE 8
29
30 #define HALTED 0
31 #define RUNNING 1
32
33 struct mc32_mailbox
34 {
35 u16 mbox;
36 u16 data[1];
37 } __attribute((packed));
38
39 struct skb_header
40 {
41 u8 status;
42 u8 control;
43 u16 next; /* Do not change! */
44 u16 length;
45 u32 data;
46 } __attribute((packed));
47
48 struct mc32_stats
49 {
50 /* RX Errors */
51 u32 rx_crc_errors;
52 u32 rx_alignment_errors;
53 u32 rx_overrun_errors;
54 u32 rx_tooshort_errors;
55 u32 rx_toolong_errors;
56 u32 rx_outofresource_errors;
57
58 u32 rx_discarded; /* via card pattern match filter */
59
60 /* TX Errors */
61 u32 tx_max_collisions;
62 u32 tx_carrier_errors;
63 u32 tx_underrun_errors;
64 u32 tx_cts_errors;
65 u32 tx_timeout_errors;
66
67 /* various cruft */
68 u32 dataA[6];
69 u16 dataB[5];
70 u32 dataC[14];
71 } __attribute((packed));
72
73 #define STATUS_MASK 0x0F
74 #define COMPLETED (1<<7)
75 #define COMPLETED_OK (1<<6)
76 #define BUFFER_BUSY (1<<5)
77
78 #define CONTROL_EOP (1<<7) /* End Of Packet */
79 #define CONTROL_EOL (1<<6) /* End of List */
80
81 #define MCA_MC32_ID 0x0041 /* Our MCA ident */
82
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