1 #ifndef _3c523_INCLUDE_
2 #define _3c523_INCLUDE_
3 /*
4 This is basically a hacked version of ni52.h, for the 3c523
5 Etherlink/MC.
6 */
7
8 /*
9 * Intel i82586 Ethernet definitions
10 *
11 * This is an extension to the Linux operating system, and is covered by the
12 * same GNU General Public License that covers that work.
13 *
14 * Copyright 1995 by Chris Beauregard (cpbeaure@undergrad.math.uwaterloo.ca)
15 *
16 * See 3c523.c for details.
17 *
18 * $Header: /home/chrisb/linux-1.2.13-3c523/drivers/net/RCS/3c523.h,v 1.6 1996/01/20 05:09:00 chrisb Exp chrisb $
19 */
20
21 /*
22 * where to find the System Configuration Pointer (SCP)
23 */
24 #define SCP_DEFAULT_ADDRESS 0xfffff4
25
26
27 /*
28 * System Configuration Pointer Struct
29 */
30
31 struct scp_struct
32 {
33 unsigned short zero_dum0; /* has to be zero */
34 unsigned char sysbus; /* 0=16Bit,1=8Bit */
35 unsigned char zero_dum1; /* has to be zero for 586 */
36 unsigned short zero_dum2;
37 unsigned short zero_dum3;
38 char *iscp; /* pointer to the iscp-block */
39 };
40
41
42 /*
43 * Intermediate System Configuration Pointer (ISCP)
44 */
45 struct iscp_struct
46 {
47 unsigned char busy; /* 586 clears after successful init */
48 unsigned char zero_dummy; /* hast to be zero */
49 unsigned short scb_offset; /* pointeroffset to the scb_base */
50 char *scb_base; /* base-address of all 16-bit offsets */
51 };
52
53 /*
54 * System Control Block (SCB)
55 */
56 struct scb_struct
57 {
58 unsigned short status; /* status word */
59 unsigned short cmd; /* command word */
60 unsigned short cbl_offset; /* pointeroffset, command block list */
61 unsigned short rfa_offset; /* pointeroffset, receive frame area */
62 unsigned short crc_errs; /* CRC-Error counter */
63 unsigned short aln_errs; /* alignmenterror counter */
64 unsigned short rsc_errs; /* Resourceerror counter */
65 unsigned short ovrn_errs; /* OVerrunerror counter */
66 };
67
68 /*
69 * possible command values for the command word
70 */
71 #define RUC_MASK 0x0070 /* mask for RU commands */
72 #define RUC_NOP 0x0000 /* NOP-command */
73 #define RUC_START 0x0010 /* start RU */
74 #define RUC_RESUME 0x0020 /* resume RU after suspend */
75 #define RUC_SUSPEND 0x0030 /* suspend RU */
76 #define RUC_ABORT 0x0040 /* abort receiver operation immediately */
77
78 #define CUC_MASK 0x0700 /* mask for CU command */
79 #define CUC_NOP 0x0000 /* NOP-command */
80 #define CUC_START 0x0100 /* start execution of 1. cmd on the CBL */
81 #define CUC_RESUME 0x0200 /* resume after suspend */
82 #define CUC_SUSPEND 0x0300 /* Suspend CU */
83 #define CUC_ABORT 0x0400 /* abort command operation immediately */
84
85 #define ACK_MASK 0xf000 /* mask for ACK command */
86 #define ACK_CX 0x8000 /* acknowledges STAT_CX */
87 #define ACK_FR 0x4000 /* ack. STAT_FR */
88 #define ACK_CNA 0x2000 /* ack. STAT_CNA */
89 #define ACK_RNR 0x1000 /* ack. STAT_RNR */
90
91 /*
92 * possible status values for the status word
93 */
94 #define STAT_MASK 0xf000 /* mask for cause of interrupt */
95 #define STAT_CX 0x8000 /* CU finished cmd with its I bit set */
96 #define STAT_FR 0x4000 /* RU finished receiving a frame */
97 #define STAT_CNA 0x2000 /* CU left active state */
98 #define STAT_RNR 0x1000 /* RU left ready state */
99
100 #define CU_STATUS 0x700 /* CU status, 0=idle */
101 #define CU_SUSPEND 0x100 /* CU is suspended */
102 #define CU_ACTIVE 0x200 /* CU is active */
103
104 #define RU_STATUS 0x70 /* RU status, 0=idle */
105 #define RU_SUSPEND 0x10 /* RU suspended */
106 #define RU_NOSPACE 0x20 /* RU no resources */
107 #define RU_READY 0x40 /* RU is ready */
108
109 /*
110 * Receive Frame Descriptor (RFD)
111 */
112 struct rfd_struct
113 {
114 unsigned short status; /* status word */
115 unsigned short last; /* Bit15,Last Frame on List / Bit14,suspend */
116 unsigned short next; /* linkoffset to next RFD */
117 unsigned short rbd_offset; /* pointeroffset to RBD-buffer */
118 unsigned char dest[6]; /* ethernet-address, destination */
119 unsigned char source[6]; /* ethernet-address, source */
120 unsigned short length; /* 802.3 frame-length */
121 unsigned short zero_dummy; /* dummy */
122 };
123
124 #define RFD_LAST 0x8000 /* last: last rfd in the list */
125 #define RFD_SUSP 0x4000 /* last: suspend RU after */
126 #define RFD_ERRMASK 0x0fe1 /* status: errormask */
127 #define RFD_MATCHADD 0x0002 /* status: Destinationaddress !matches IA */
128 #define RFD_RNR 0x0200 /* status: receiver out of resources */
129
130 /*
131 * Receive Buffer Descriptor (RBD)
132 */
133 struct rbd_struct
134 {
135 unsigned short status; /* status word,number of used bytes in buff */
136 unsigned short next; /* pointeroffset to next RBD */
137 char *buffer; /* receive buffer address pointer */
138 unsigned short size; /* size of this buffer */
139 unsigned short zero_dummy; /* dummy */
140 };
141
142 #define RBD_LAST 0x8000 /* last buffer */
143 #define RBD_USED 0x4000 /* this buffer has data */
144 #define RBD_MASK 0x3fff /* size-mask for length */
145
146 /*
147 * Statusvalues for Commands/RFD
148 */
149 #define STAT_COMPL 0x8000 /* status: frame/command is complete */
150 #define STAT_BUSY 0x4000 /* status: frame/command is busy */
151 #define STAT_OK 0x2000 /* status: frame/command is ok */
152
153 /*
154 * Action-Commands
155 */
156 #define CMD_NOP 0x0000 /* NOP */
157 #define CMD_IASETUP 0x0001 /* initial address setup command */
158 #define CMD_CONFIGURE 0x0002 /* configure command */
159 #define CMD_MCSETUP 0x0003 /* MC setup command */
160 #define CMD_XMIT 0x0004 /* transmit command */
161 #define CMD_TDR 0x0005 /* time domain reflectometer (TDR) command */
162 #define CMD_DUMP 0x0006 /* dump command */
163 #define CMD_DIAGNOSE 0x0007 /* diagnose command */
164
165 /*
166 * Action command bits
167 */
168 #define CMD_LAST 0x8000 /* indicates last command in the CBL */
169 #define CMD_SUSPEND 0x4000 /* suspend CU after this CB */
170 #define CMD_INT 0x2000 /* generate interrupt after execution */
171
172 /*
173 * NOP - command
174 */
175 struct nop_cmd_struct
176 {
177 unsigned short cmd_status; /* status of this command */
178 unsigned short cmd_cmd; /* the command itself (+bits) */
179 unsigned short cmd_link; /* offsetpointer to next command */
180 };
181
182 /*
183 * IA Setup command
184 */
185 struct iasetup_cmd_struct
186 {
187 unsigned short cmd_status;
188 unsigned short cmd_cmd;
189 unsigned short cmd_link;
190 unsigned char iaddr[6];
191 };
192
193 /*
194 * Configure command
195 */
196 struct configure_cmd_struct
197 {
198 unsigned short cmd_status;
199 unsigned short cmd_cmd;
200 unsigned short cmd_link;
201 unsigned char byte_cnt; /* size of the config-cmd */
202 unsigned char fifo; /* fifo/recv monitor */
203 unsigned char sav_bf; /* save bad frames (bit7=1)*/
204 unsigned char adr_len; /* adr_len(0-2),al_loc(3),pream(4-5),loopbak(6-7)*/
205 unsigned char priority; /* lin_prio(0-2),exp_prio(4-6),bof_metd(7) */
206 unsigned char ifs; /* inter frame spacing */
207 unsigned char time_low; /* slot time low */
208 unsigned char time_high; /* slot time high(0-2) and max. retries(4-7) */
209 unsigned char promisc; /* promisc-mode(0) , et al (1-7) */
210 unsigned char carr_coll; /* carrier(0-3)/collision(4-7) stuff */
211 unsigned char fram_len; /* minimal frame len */
212 unsigned char dummy; /* dummy */
213 };
214
215 /*
216 * Multicast Setup command
217 */
218 struct mcsetup_cmd_struct
219 {
220 unsigned short cmd_status;
221 unsigned short cmd_cmd;
222 unsigned short cmd_link;
223 unsigned short mc_cnt; /* number of bytes in the MC-List */
224 unsigned char mc_list[0][6]; /* pointer to 6 bytes entries */
225 };
226
227 /*
228 * transmit command
229 */
230 struct transmit_cmd_struct
231 {
232 unsigned short cmd_status;
233 unsigned short cmd_cmd;
234 unsigned short cmd_link;
235 unsigned short tbd_offset; /* pointeroffset to TBD */
236 unsigned char dest[6]; /* destination address of the frame */
237 unsigned short length; /* user defined: 802.3 length / Ether type */
238 };
239
240 #define TCMD_ERRMASK 0x0fa0
241 #define TCMD_MAXCOLLMASK 0x000f
242 #define TCMD_MAXCOLL 0x0020
243 #define TCMD_HEARTBEAT 0x0040
244 #define TCMD_DEFERRED 0x0080
245 #define TCMD_UNDERRUN 0x0100
246 #define TCMD_LOSTCTS 0x0200
247 #define TCMD_NOCARRIER 0x0400
248 #define TCMD_LATECOLL 0x0800
249
250 struct tdr_cmd_struct
251 {
252 unsigned short cmd_status;
253 unsigned short cmd_cmd;
254 unsigned short cmd_link;
255 unsigned short status;
256 };
257
258 #define TDR_LNK_OK 0x8000 /* No link problem identified */
259 #define TDR_XCVR_PRB 0x4000 /* indicates a transceiver problem */
260 #define TDR_ET_OPN 0x2000 /* open, no correct termination */
261 #define TDR_ET_SRT 0x1000 /* TDR detected a short circuit */
262 #define TDR_TIMEMASK 0x07ff /* mask for the time field */
263
264 /*
265 * Transmit Buffer Descriptor (TBD)
266 */
267 struct tbd_struct
268 {
269 unsigned short size; /* size + EOF-Flag(15) */
270 unsigned short next; /* pointeroffset to next TBD */
271 char *buffer; /* pointer to buffer */
272 };
273
274 #define TBD_LAST 0x8000 /* EOF-Flag, indicates last buffer in list */
275
276 /*************************************************************************/
277 /*
278 Verbatim from the Crynwyr stuff:
279
280 The 3c523 responds with adapter code 0x6042 at slot
281 registers xxx0 and xxx1. The setup register is at xxx2 and
282 contains the following bits:
283
284 0: card enable
285 2,1: csr address select
286 00 = 0300
287 01 = 1300
288 10 = 2300
289 11 = 3300
290 4,3: shared memory address select
291 00 = 0c0000
292 01 = 0c8000
293 10 = 0d0000
294 11 = 0d8000
295 5: set to disable on-board thinnet
296 7,6: (read-only) shows selected irq
297 00 = 12
298 01 = 7
299 10 = 3
300 11 = 9
301
302 The interrupt-select register is at xxx3 and uses one bit per irq.
303
304 0: int 12
305 1: int 7
306 2: int 3
307 3: int 9
308
309 Again, the documentation stresses that the setup register
310 should never be written. The interrupt-select register may be
311 written with the value corresponding to bits 7.6 in
312 the setup register to insure corret setup.
313 */
314
315 /* Offsets from the base I/O address. */
316 #define ELMC_SA 0 /* first 6 bytes are IEEE network address */
317 #define ELMC_CTRL 6 /* control & status register */
318 #define ELMC_REVISION 7 /* revision register, first 4 bits only */
319 #define ELMC_IO_EXTENT 8
320
321 /* these are the bit selects for the port register 2 */
322 #define ELMC_STATUS_ENABLED 0x01
323 #define ELMC_STATUS_CSR_SELECT 0x06
324 #define ELMC_STATUS_MEMORY_SELECT 0x18
325 #define ELMC_STATUS_DISABLE_THIN 0x20
326 #define ELMC_STATUS_IRQ_SELECT 0xc0
327
328 /* this is the card id used in the detection code. You might recognize
329 it from @6042.adf */
330 #define ELMC_MCA_ID 0x6042
331
332 /*
333 The following define the bits for the control & status register
334
335 The bank select registers can be used if more than 16K of memory is
336 on the card. For some stupid reason, bank 3 is the one for the
337 bottom 16K, and the card defaults to bank 0. So we have to set the
338 bank to 3 before the card will even think of operating. To get bank
339 3, set BS0 and BS1 to high (of course...)
340 */
341 #define ELMC_CTRL_BS0 0x01 /* RW bank select */
342 #define ELMC_CTRL_BS1 0x02 /* RW bank select */
343 #define ELMC_CTRL_INTE 0x04 /* RW interrupt enable, assert high */
344 #define ELMC_CTRL_INT 0x08 /* R interrupt active, assert high */
345 /*#define ELMC_CTRL_* 0x10*/ /* reserved */
346 #define ELMC_CTRL_LBK 0x20 /* RW loopback enable, assert high */
347 #define ELMC_CTRL_CA 0x40 /* RW channel attention, assert high */
348 #define ELMC_CTRL_RST 0x80 /* RW 82586 reset, assert low */
349
350 /* some handy compound bits */
351
352 /* normal operation should have bank 3 and RST high, ints enabled */
353 #define ELMC_NORMAL (ELMC_CTRL_INTE|ELMC_CTRL_RST|0x3)
354
355 #endif /* _3c523_INCLUDE_ */
356
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