1 /*
2 * video1394.c - video driver for OHCI 1394 boards
3 * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au>
4 * Peter Schlaile <udbz@rz.uni-karlsruhe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * NOTES:
21 *
22 * ioctl return codes:
23 * EFAULT is only for invalid address for the argp
24 * EINVAL for out of range values
25 * EBUSY when trying to use an already used resource
26 * ESRCH when trying to free/stop a not used resource
27 * EAGAIN for resource allocation failure that could perhaps succeed later
28 * ENOTTY for unsupported ioctl request
29 *
30 */
31 #include <linux/config.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/slab.h>
35 #include <linux/interrupt.h>
36 #include <linux/wait.h>
37 #include <linux/errno.h>
38 #include <linux/module.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
41 #include <linux/fs.h>
42 #include <linux/poll.h>
43 #include <linux/smp_lock.h>
44 #include <linux/delay.h>
45 #include <linux/bitops.h>
46 #include <linux/types.h>
47 #include <linux/vmalloc.h>
48 #include <linux/timex.h>
49 #include <linux/mm.h>
50 #include <linux/compat.h>
51 #include <linux/cdev.h>
52
53 #include "ieee1394.h"
54 #include "ieee1394_types.h"
55 #include "hosts.h"
56 #include "ieee1394_core.h"
57 #include "highlevel.h"
58 #include "video1394.h"
59 #include "nodemgr.h"
60 #include "dma.h"
61
62 #include "ohci1394.h"
63
64 #define ISO_CHANNELS 64
65
66 struct it_dma_prg {
67 struct dma_cmd begin;
68 quadlet_t data[4];
69 struct dma_cmd end;
70 quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */
71 };
72
73 struct dma_iso_ctx {
74 struct ti_ohci *ohci;
75 int type; /* OHCI_ISO_TRANSMIT or OHCI_ISO_RECEIVE */
76 struct ohci1394_iso_tasklet iso_tasklet;
77 int channel;
78 int ctx;
79 int last_buffer;
80 int * next_buffer; /* For ISO Transmit of video packets
81 to write the correct SYT field
82 into the next block */
83 unsigned int num_desc;
84 unsigned int buf_size;
85 unsigned int frame_size;
86 unsigned int packet_size;
87 unsigned int left_size;
88 unsigned int nb_cmd;
89
90 struct dma_region dma;
91
92 struct dma_prog_region *prg_reg;
93
94 struct dma_cmd **ir_prg;
95 struct it_dma_prg **it_prg;
96
97 unsigned int *buffer_status;
98 unsigned int *buffer_prg_assignment;
99 struct timeval *buffer_time; /* time when the buffer was received */
100 unsigned int *last_used_cmd; /* For ISO Transmit with
101 variable sized packets only ! */
102 int ctrlClear;
103 int ctrlSet;
104 int cmdPtr;
105 int ctxMatch;
106 wait_queue_head_t waitq;
107 spinlock_t lock;
108 unsigned int syt_offset;
109 int flags;
110
111 struct list_head link;
112 };
113
114
115 struct file_ctx {
116 struct ti_ohci *ohci;
117 struct list_head context_list;
118 struct dma_iso_ctx *current_ctx;
119 };
120
121 #ifdef CONFIG_IEEE1394_VERBOSEDEBUG
122 #define VIDEO1394_DEBUG
123 #endif
124
125 #ifdef DBGMSG
126 #undef DBGMSG
127 #endif
128
129 #ifdef VIDEO1394_DEBUG
130 #define DBGMSG(card, fmt, args...) \
131 printk(KERN_INFO "video1394_%d: " fmt "\n" , card , ## args)
132 #else
133 #define DBGMSG(card, fmt, args...)
134 #endif
135
136 /* print general (card independent) information */
137 #define PRINT_G(level, fmt, args...) \
138 printk(level "video1394: " fmt "\n" , ## args)
139
140 /* print card specific information */
141 #define PRINT(level, card, fmt, args...) \
142 printk(level "video1394_%d: " fmt "\n" , card , ## args)
143
144 static void wakeup_dma_ir_ctx(unsigned long l);
145 static void wakeup_dma_it_ctx(unsigned long l);
146
147 static struct hpsb_highlevel video1394_highlevel;
148
149 static int free_dma_iso_ctx(struct dma_iso_ctx *d)
150 {
151 int i;
152
153 DBGMSG(d->ohci->host->id, "Freeing dma_iso_ctx %d", d->ctx);
154
155 ohci1394_stop_context(d->ohci, d->ctrlClear, NULL);
156 if (d->iso_tasklet.link.next != NULL)
157 ohci1394_unregister_iso_tasklet(d->ohci, &d->iso_tasklet);
158
159 dma_region_free(&d->dma);
160
161 if (d->prg_reg) {
162 for (i = 0; i < d->num_desc; i++)
163 dma_prog_region_free(&d->prg_reg[i]);
164 kfree(d->prg_reg);
165 }
166
167 kfree(d->ir_prg);
168 kfree(d->it_prg);
169 kfree(d->buffer_status);
170 kfree(d->buffer_prg_assignment);
171 kfree(d->buffer_time);
172 kfree(d->last_used_cmd);
173 kfree(d->next_buffer);
174 list_del(&d->link);
175 kfree(d);
176
177 return 0;
178 }
179
180 static struct dma_iso_ctx *
181 alloc_dma_iso_ctx(struct ti_ohci *ohci, int type, int num_desc,
182 int buf_size, int channel, unsigned int packet_size)
183 {
184 struct dma_iso_ctx *d;
185 int i;
186
187 d = kzalloc(sizeof(*d), GFP_KERNEL);
188 if (!d) {
189 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma_iso_ctx");
190 return NULL;
191 }
192
193 d->ohci = ohci;
194 d->type = type;
195 d->channel = channel;
196 d->num_desc = num_desc;
197 d->frame_size = buf_size;
198 d->buf_size = PAGE_ALIGN(buf_size);
199 d->last_buffer = -1;
200 INIT_LIST_HEAD(&d->link);
201 init_waitqueue_head(&d->waitq);
202
203 /* Init the regions for easy cleanup */
204 dma_region_init(&d->dma);
205
206 if (dma_region_alloc(&d->dma, (d->num_desc - 1) * d->buf_size, ohci->dev,
207 PCI_DMA_BIDIRECTIONAL)) {
208 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma buffer");
209 free_dma_iso_ctx(d);
210 return NULL;
211 }
212
213 if (type == OHCI_ISO_RECEIVE)
214 ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
215 wakeup_dma_ir_ctx,
216 (unsigned long) d);
217 else
218 ohci1394_init_iso_tasklet(&d->iso_tasklet, type,
219 wakeup_dma_it_ctx,
220 (unsigned long) d);
221
222 if (ohci1394_register_iso_tasklet(ohci, &d->iso_tasklet) < 0) {
223 PRINT(KERN_ERR, ohci->host->id, "no free iso %s contexts",
224 type == OHCI_ISO_RECEIVE ? "receive" : "transmit");
225 free_dma_iso_ctx(d);
226 return NULL;
227 }
228 d->ctx = d->iso_tasklet.context;
229
230 d->prg_reg = kmalloc(d->num_desc * sizeof(*d->prg_reg), GFP_KERNEL);
231 if (!d->prg_reg) {
232 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate ir prg regs");
233 free_dma_iso_ctx(d);
234 return NULL;
235 }
236 /* Makes for easier cleanup */
237 for (i = 0; i < d->num_desc; i++)
238 dma_prog_region_init(&d->prg_reg[i]);
239
240 if (type == OHCI_ISO_RECEIVE) {
241 d->ctrlSet = OHCI1394_IsoRcvContextControlSet+32*d->ctx;
242 d->ctrlClear = OHCI1394_IsoRcvContextControlClear+32*d->ctx;
243 d->cmdPtr = OHCI1394_IsoRcvCommandPtr+32*d->ctx;
244 d->ctxMatch = OHCI1394_IsoRcvContextMatch+32*d->ctx;
245
246 d->ir_prg = kzalloc(d->num_desc * sizeof(*d->ir_prg),
247 GFP_KERNEL);
248
249 if (!d->ir_prg) {
250 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
251 free_dma_iso_ctx(d);
252 return NULL;
253 }
254
255 d->nb_cmd = d->buf_size / PAGE_SIZE + 1;
256 d->left_size = (d->frame_size % PAGE_SIZE) ?
257 d->frame_size % PAGE_SIZE : PAGE_SIZE;
258
259 for (i = 0;i < d->num_desc; i++) {
260 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
261 sizeof(struct dma_cmd), ohci->dev)) {
262 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma ir prg");
263 free_dma_iso_ctx(d);
264 return NULL;
265 }
266 d->ir_prg[i] = (struct dma_cmd *)d->prg_reg[i].kvirt;
267 }
268
269 } else { /* OHCI_ISO_TRANSMIT */
270 d->ctrlSet = OHCI1394_IsoXmitContextControlSet+16*d->ctx;
271 d->ctrlClear = OHCI1394_IsoXmitContextControlClear+16*d->ctx;
272 d->cmdPtr = OHCI1394_IsoXmitCommandPtr+16*d->ctx;
273
274 d->it_prg = kzalloc(d->num_desc * sizeof(*d->it_prg),
275 GFP_KERNEL);
276
277 if (!d->it_prg) {
278 PRINT(KERN_ERR, ohci->host->id,
279 "Failed to allocate dma it prg");
280 free_dma_iso_ctx(d);
281 return NULL;
282 }
283
284 d->packet_size = packet_size;
285
286 if (PAGE_SIZE % packet_size || packet_size>4096) {
287 PRINT(KERN_ERR, ohci->host->id,
288 "Packet size %d (page_size: %ld) "
289 "not yet supported\n",
290 packet_size, PAGE_SIZE);
291 free_dma_iso_ctx(d);
292 return NULL;
293 }
294
295 d->nb_cmd = d->frame_size / d->packet_size;
296 if (d->frame_size % d->packet_size) {
297 d->nb_cmd++;
298 d->left_size = d->frame_size % d->packet_size;
299 } else
300 d->left_size = d->packet_size;
301
302 for (i = 0; i < d->num_desc; i++) {
303 if (dma_prog_region_alloc(&d->prg_reg[i], d->nb_cmd *
304 sizeof(struct it_dma_prg), ohci->dev)) {
305 PRINT(KERN_ERR, ohci->host->id, "Failed to allocate dma it prg");
306 free_dma_iso_ctx(d);
307 return NULL;
308 }
309 d->it_prg[i] = (struct it_dma_prg *)d->prg_reg[i].kvirt;
310 }
311 }
312
313 d->buffer_status =
314 kzalloc(d->num_desc * sizeof(*d->buffer_status), GFP_KERNEL);
315 d->buffer_prg_assignment =
316 kzalloc(d->num_desc * sizeof(*d->buffer_prg_assignment), GFP_KERNEL);
317 d->buffer_time =
318 kzalloc(d->num_desc * sizeof(*d->buffer_time), GFP_KERNEL);
319 d->last_used_cmd =
320 kzalloc(d->num_desc * sizeof(*d->last_used_cmd), GFP_KERNEL);
321 d->next_buffer =
322 kzalloc(d->num_desc * sizeof(*d->next_buffer), GFP_KERNEL);
323
324 if (!d->buffer_status || !d->buffer_prg_assignment || !d->buffer_time ||
325 !d->last_used_cmd || !d->next_buffer) {
326 PRINT(KERN_ERR, ohci->host->id,
327 "Failed to allocate dma_iso_ctx member");
328 free_dma_iso_ctx(d);
329 return NULL;
330 }
331
332 spin_lock_init(&d->lock);
333
334 PRINT(KERN_INFO, ohci->host->id, "Iso %s DMA: %d buffers "
335 "of size %d allocated for a frame size %d, each with %d prgs",
336 (type == OHCI_ISO_RECEIVE) ? "receive" : "transmit",
337 d->num_desc - 1, d->buf_size, d->frame_size, d->nb_cmd);
338
339 return d;
340 }
341
342 static void reset_ir_status(struct dma_iso_ctx *d, int n)
343 {
344 int i;
345 d->ir_prg[n][0].status = cpu_to_le32(4);
346 d->ir_prg[n][1].status = cpu_to_le32(PAGE_SIZE-4);
347 for (i = 2; i < d->nb_cmd - 1; i++)
348 d->ir_prg[n][i].status = cpu_to_le32(PAGE_SIZE);
349 d->ir_prg[n][i].status = cpu_to_le32(d->left_size);
350 }
351
352 static void reprogram_dma_ir_prg(struct dma_iso_ctx *d, int n, int buffer, int flags)
353 {
354 struct dma_cmd *ir_prg = d->ir_prg[n];
355 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
356 int i;
357
358 d->buffer_prg_assignment[n] = buffer;
359
360 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
361 (unsigned long)d->dma.kvirt));
362 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
363 (buf + 4) - (unsigned long)d->dma.kvirt));
364
365 for (i=2;i<d->nb_cmd-1;i++) {
366 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
367 (buf+(i-1)*PAGE_SIZE) -
368 (unsigned long)d->dma.kvirt));
369 }
370
371 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
372 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
373 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
374 (buf+(i-1)*PAGE_SIZE) - (unsigned long)d->dma.kvirt));
375 }
376
377 static void initialize_dma_ir_prg(struct dma_iso_ctx *d, int n, int flags)
378 {
379 struct dma_cmd *ir_prg = d->ir_prg[n];
380 struct dma_prog_region *ir_reg = &d->prg_reg[n];
381 unsigned long buf = (unsigned long)d->dma.kvirt;
382 int i;
383
384 /* the first descriptor will read only 4 bytes */
385 ir_prg[0].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
386 DMA_CTL_BRANCH | 4);
387
388 /* set the sync flag */
389 if (flags & VIDEO1394_SYNC_FRAMES)
390 ir_prg[0].control |= cpu_to_le32(DMA_CTL_WAIT);
391
392 ir_prg[0].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, buf -
393 (unsigned long)d->dma.kvirt));
394 ir_prg[0].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
395 1 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
396
397 /* If there is *not* only one DMA page per frame (hence, d->nb_cmd==2) */
398 if (d->nb_cmd > 2) {
399 /* The second descriptor will read PAGE_SIZE-4 bytes */
400 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
401 DMA_CTL_BRANCH | (PAGE_SIZE-4));
402 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf + 4) -
403 (unsigned long)d->dma.kvirt));
404 ir_prg[1].branchAddress = cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
405 2 * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
406
407 for (i = 2; i < d->nb_cmd - 1; i++) {
408 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
409 DMA_CTL_BRANCH | PAGE_SIZE);
410 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
411 (buf+(i-1)*PAGE_SIZE) -
412 (unsigned long)d->dma.kvirt));
413
414 ir_prg[i].branchAddress =
415 cpu_to_le32((dma_prog_region_offset_to_bus(ir_reg,
416 (i + 1) * sizeof(struct dma_cmd)) & 0xfffffff0) | 0x1);
417 }
418
419 /* The last descriptor will generate an interrupt */
420 ir_prg[i].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
421 DMA_CTL_IRQ | DMA_CTL_BRANCH | d->left_size);
422 ir_prg[i].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
423 (buf+(i-1)*PAGE_SIZE) -
424 (unsigned long)d->dma.kvirt));
425 } else {
426 /* Only one DMA page is used. Read d->left_size immediately and */
427 /* generate an interrupt as this is also the last page. */
428 ir_prg[1].control = cpu_to_le32(DMA_CTL_INPUT_MORE | DMA_CTL_UPDATE |
429 DMA_CTL_IRQ | DMA_CTL_BRANCH | (d->left_size-4));
430 ir_prg[1].address = cpu_to_le32(dma_region_offset_to_bus(&d->dma,
431 (buf + 4) - (unsigned long)d->dma.kvirt));
432 }
433 }
434
435 static void initialize_dma_ir_ctx(struct dma_iso_ctx *d, int tag, int flags)
436 {
437 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
438 int i;
439
440 d->flags = flags;
441
442 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
443
444 for (i=0;i<d->num_desc;i++) {
445 initialize_dma_ir_prg(d, i, flags);
446 reset_ir_status(d, i);
447 }
448
449 /* reset the ctrl register */
450 reg_write(ohci, d->ctrlClear, 0xf0000000);
451
452 /* Set bufferFill */
453 reg_write(ohci, d->ctrlSet, 0x80000000);
454
455 /* Set isoch header */
456 if (flags & VIDEO1394_INCLUDE_ISO_HEADERS)
457 reg_write(ohci, d->ctrlSet, 0x40000000);
458
459 /* Set the context match register to match on all tags,
460 sync for sync tag, and listen to d->channel */
461 reg_write(ohci, d->ctxMatch, 0xf0000000|((tag&0xf)<<8)|d->channel);
462
463 /* Set up isoRecvIntMask to generate interrupts */
464 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1<<d->ctx);
465 }
466
467 /* find which context is listening to this channel */
468 static struct dma_iso_ctx *
469 find_ctx(struct list_head *list, int type, int channel)
470 {
471 struct dma_iso_ctx *ctx;
472
473 list_for_each_entry(ctx, list, link) {
474 if (ctx->type == type && ctx->channel == channel)
475 return ctx;
476 }
477
478 return NULL;
479 }
480
481 static void wakeup_dma_ir_ctx(unsigned long l)
482 {
483 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
484 int i;
485
486 spin_lock(&d->lock);
487
488 for (i = 0; i < d->num_desc; i++) {
489 if (d->ir_prg[i][d->nb_cmd-1].status & cpu_to_le32(0xFFFF0000)) {
490 reset_ir_status(d, i);
491 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
492 do_gettimeofday(&d->buffer_time[d->buffer_prg_assignment[i]]);
493 }
494 }
495
496 spin_unlock(&d->lock);
497
498 if (waitqueue_active(&d->waitq))
499 wake_up_interruptible(&d->waitq);
500 }
501
502 static inline void put_timestamp(struct ti_ohci *ohci, struct dma_iso_ctx * d,
503 int n)
504 {
505 unsigned char* buf = d->dma.kvirt + n * d->buf_size;
506 u32 cycleTimer;
507 u32 timeStamp;
508
509 if (n == -1) {
510 return;
511 }
512
513 cycleTimer = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
514
515 timeStamp = ((cycleTimer & 0x0fff) + d->syt_offset); /* 11059 = 450 us */
516 timeStamp = (timeStamp % 3072 + ((timeStamp / 3072) << 12)
517 + (cycleTimer & 0xf000)) & 0xffff;
518
519 buf[6] = timeStamp >> 8;
520 buf[7] = timeStamp & 0xff;
521
522 /* if first packet is empty packet, then put timestamp into the next full one too */
523 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
524 buf += d->packet_size;
525 buf[6] = timeStamp >> 8;
526 buf[7] = timeStamp & 0xff;
527 }
528
529 /* do the next buffer frame too in case of irq latency */
530 n = d->next_buffer[n];
531 if (n == -1) {
532 return;
533 }
534 buf = d->dma.kvirt + n * d->buf_size;
535
536 timeStamp += (d->last_used_cmd[n] << 12) & 0xffff;
537
538 buf[6] = timeStamp >> 8;
539 buf[7] = timeStamp & 0xff;
540
541 /* if first packet is empty packet, then put timestamp into the next full one too */
542 if ( (le32_to_cpu(d->it_prg[n][0].data[1]) >>16) == 0x008) {
543 buf += d->packet_size;
544 buf[6] = timeStamp >> 8;
545 buf[7] = timeStamp & 0xff;
546 }
547
548 #if 0
549 printk("curr: %d, next: %d, cycleTimer: %08x timeStamp: %08x\n",
550 curr, n, cycleTimer, timeStamp);
551 #endif
552 }
553
554 static void wakeup_dma_it_ctx(unsigned long l)
555 {
556 struct dma_iso_ctx *d = (struct dma_iso_ctx *) l;
557 struct ti_ohci *ohci = d->ohci;
558 int i;
559
560 spin_lock(&d->lock);
561
562 for (i = 0; i < d->num_desc; i++) {
563 if (d->it_prg[i][d->last_used_cmd[i]].end.status &
564 cpu_to_le32(0xFFFF0000)) {
565 int next = d->next_buffer[i];
566 put_timestamp(ohci, d, next);
567 d->it_prg[i][d->last_used_cmd[i]].end.status = 0;
568 d->buffer_status[d->buffer_prg_assignment[i]] = VIDEO1394_BUFFER_READY;
569 }
570 }
571
572 spin_unlock(&d->lock);
573
574 if (waitqueue_active(&d->waitq))
575 wake_up_interruptible(&d->waitq);
576 }
577
578 static void reprogram_dma_it_prg(struct dma_iso_ctx *d, int n, int buffer)
579 {
580 struct it_dma_prg *it_prg = d->it_prg[n];
581 unsigned long buf = (unsigned long)d->dma.kvirt + buffer * d->buf_size;
582 int i;
583
584 d->buffer_prg_assignment[n] = buffer;
585 for (i=0;i<d->nb_cmd;i++) {
586 it_prg[i].end.address =
587 cpu_to_le32(dma_region_offset_to_bus(&d->dma,
588 (buf+i*d->packet_size) - (unsigned long)d->dma.kvirt));
589 }
590 }
591
592 static void initialize_dma_it_prg(struct dma_iso_ctx *d, int n, int sync_tag)
593 {
594 struct it_dma_prg *it_prg = d->it_prg[n];
595 struct dma_prog_region *it_reg = &d->prg_reg[n];
596 unsigned long buf = (unsigned long)d->dma.kvirt;
597 int i;
598 d->last_used_cmd[n] = d->nb_cmd - 1;
599 for (i=0;i<d->nb_cmd;i++) {
600
601 it_prg[i].begin.control = cpu_to_le32(DMA_CTL_OUTPUT_MORE |
602 DMA_CTL_IMMEDIATE | 8) ;
603 it_prg[i].begin.address = 0;
604
605 it_prg[i].begin.status = 0;
606
607 it_prg[i].data[0] = cpu_to_le32(
608 (IEEE1394_SPEED_100 << 16)
609 | (/* tag */ 1 << 14)
610 | (d->channel << 8)
611 | (TCODE_ISO_DATA << 4));
612 if (i==0) it_prg[i].data[0] |= cpu_to_le32(sync_tag);
613 it_prg[i].data[1] = cpu_to_le32(d->packet_size << 16);
614 it_prg[i].data[2] = 0;
615 it_prg[i].data[3] = 0;
616
617 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST |
618 DMA_CTL_BRANCH);
619 it_prg[i].end.address =
620 cpu_to_le32(dma_region_offset_to_bus(&d->dma, (buf+i*d->packet_size) -
621 (unsigned long)d->dma.kvirt));
622
623 if (i<d->nb_cmd-1) {
624 it_prg[i].end.control |= cpu_to_le32(d->packet_size);
625 it_prg[i].begin.branchAddress =
626 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
627 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
628 it_prg[i].end.branchAddress =
629 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
630 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
631 } else {
632 /* the last prg generates an interrupt */
633 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
634 DMA_CTL_IRQ | d->left_size);
635 /* the last prg doesn't branch */
636 it_prg[i].begin.branchAddress = 0;
637 it_prg[i].end.branchAddress = 0;
638 }
639 it_prg[i].end.status = 0;
640 }
641 }
642
643 static void initialize_dma_it_prg_var_packet_queue(
644 struct dma_iso_ctx *d, int n, unsigned int * packet_sizes,
645 struct ti_ohci *ohci)
646 {
647 struct it_dma_prg *it_prg = d->it_prg[n];
648 struct dma_prog_region *it_reg = &d->prg_reg[n];
649 int i;
650
651 #if 0
652 if (n != -1) {
653 put_timestamp(ohci, d, n);
654 }
655 #endif
656 d->last_used_cmd[n] = d->nb_cmd - 1;
657
658 for (i = 0; i < d->nb_cmd; i++) {
659 unsigned int size;
660 if (packet_sizes[i] > d->packet_size) {
661 size = d->packet_size;
662 } else {
663 size = packet_sizes[i];
664 }
665 it_prg[i].data[1] = cpu_to_le32(size << 16);
666 it_prg[i].end.control = cpu_to_le32(DMA_CTL_OUTPUT_LAST | DMA_CTL_BRANCH);
667
668 if (i < d->nb_cmd-1 && packet_sizes[i+1] != 0) {
669 it_prg[i].end.control |= cpu_to_le32(size);
670 it_prg[i].begin.branchAddress =
671 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
672 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
673 it_prg[i].end.branchAddress =
674 cpu_to_le32((dma_prog_region_offset_to_bus(it_reg, (i + 1) *
675 sizeof(struct it_dma_prg)) & 0xfffffff0) | 0x3);
676 } else {
677 /* the last prg generates an interrupt */
678 it_prg[i].end.control |= cpu_to_le32(DMA_CTL_UPDATE |
679 DMA_CTL_IRQ | size);
680 /* the last prg doesn't branch */
681 it_prg[i].begin.branchAddress = 0;
682 it_prg[i].end.branchAddress = 0;
683 d->last_used_cmd[n] = i;
684 break;
685 }
686 }
687 }
688
689 static void initialize_dma_it_ctx(struct dma_iso_ctx *d, int sync_tag,
690 unsigned int syt_offset, int flags)
691 {
692 struct ti_ohci *ohci = (struct ti_ohci *)d->ohci;
693 int i;
694
695 d->flags = flags;
696 d->syt_offset = (syt_offset == 0 ? 11000 : syt_offset);
697
698 ohci1394_stop_context(ohci, d->ctrlClear, NULL);
699
700 for (i=0;i<d->num_desc;i++)
701 initialize_dma_it_prg(d, i, sync_tag);
702
703 /* Set up isoRecvIntMask to generate interrupts */
704 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1<<d->ctx);
705 }
706
707 static inline unsigned video1394_buffer_state(struct dma_iso_ctx *d,
708 unsigned int buffer)
709 {
710 unsigned long flags;
711 unsigned int ret;
712 spin_lock_irqsave(&d->lock, flags);
713 ret = d->buffer_status[buffer];
714 spin_unlock_irqrestore(&d->lock, flags);
715 return ret;
716 }
717
718 static int __video1394_ioctl(struct file *file,
719 unsigned int cmd, unsigned long arg)
720 {
721 struct file_ctx *ctx = (struct file_ctx *)file->private_data;
722 struct ti_ohci *ohci = ctx->ohci;
723 unsigned long flags;
724 void __user *argp = (void __user *)arg;
725
726 switch(cmd)
727 {
728 case VIDEO1394_IOC_LISTEN_CHANNEL:
729 case VIDEO1394_IOC_TALK_CHANNEL:
730 {
731 struct video1394_mmap v;
732 u64 mask;
733 struct dma_iso_ctx *d;
734 int i;
735
736 if (copy_from_user(&v, argp, sizeof(v)))
737 return -EFAULT;
738
739 /* if channel < 0, find lowest available one */
740 if (v.channel < 0) {
741 mask = (u64)0x1;
742 for (i=0; ; i++) {
743 if (i == ISO_CHANNELS) {
744 PRINT(KERN_ERR, ohci->host->id,
745 "No free channel found");
746 return -EAGAIN;
747 }
748 if (!(ohci->ISO_channel_usage & mask)) {
749 v.channel = i;
750 PRINT(KERN_INFO, ohci->host->id, "Found free channel %d", i);
751 break;
752 }
753 mask = mask << 1;
754 }
755 } else if (v.channel >= ISO_CHANNELS) {
756 PRINT(KERN_ERR, ohci->host->id,
757 "Iso channel %d out of bounds", v.channel);
758 return -EINVAL;
759 } else {
760 mask = (u64)0x1<<v.channel;
761 }
762 PRINT(KERN_INFO, ohci->host->id, "mask: %08X%08X usage: %08X%08X\n",
763 (u32)(mask>>32),(u32)(mask&0xffffffff),
764 (u32)(ohci->ISO_channel_usage>>32),
765 (u32)(ohci->ISO_channel_usage&0xffffffff));
766 if (ohci->ISO_channel_usage & mask) {
767 PRINT(KERN_ERR, ohci->host->id,
768 "Channel %d is already taken", v.channel);
769 return -EBUSY;
770 }
771
772 if (v.buf_size == 0 || v.buf_size > VIDEO1394_MAX_SIZE) {
773 PRINT(KERN_ERR, ohci->host->id,
774 "Invalid %d length buffer requested",v.buf_size);
775 return -EINVAL;
776 }
777
778 if (v.nb_buffers == 0 || v.nb_buffers > VIDEO1394_MAX_SIZE) {
779 PRINT(KERN_ERR, ohci->host->id,
780 "Invalid %d buffers requested",v.nb_buffers);
781 return -EINVAL;
782 }
783
784 if (v.nb_buffers * v.buf_size > VIDEO1394_MAX_SIZE) {
785 PRINT(KERN_ERR, ohci->host->id,
786 "%d buffers of size %d bytes is too big",
787 v.nb_buffers, v.buf_size);
788 return -EINVAL;
789 }
790
791 if (cmd == VIDEO1394_IOC_LISTEN_CHANNEL) {
792 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_RECEIVE,
793 v.nb_buffers + 1, v.buf_size,
794 v.channel, 0);
795
796 if (d == NULL) {
797 PRINT(KERN_ERR, ohci->host->id,
798 "Couldn't allocate ir context");
799 return -EAGAIN;
800 }
801 initialize_dma_ir_ctx(d, v.sync_tag, v.flags);
802
803 ctx->current_ctx = d;
804
805 v.buf_size = d->buf_size;
806 list_add_tail(&d->link, &ctx->context_list);
807
808 PRINT(KERN_INFO, ohci->host->id,
809 "iso context %d listen on channel %d",
810 d->ctx, v.channel);
811 }
812 else {
813 d = alloc_dma_iso_ctx(ohci, OHCI_ISO_TRANSMIT,
814 v.nb_buffers + 1, v.buf_size,
815 v.channel, v.packet_size);
816
817 if (d == NULL) {
818 PRINT(KERN_ERR, ohci->host->id,
819 "Couldn't allocate it context");
820 return -EAGAIN;
821 }
822 initialize_dma_it_ctx(d, v.sync_tag,
823 v.syt_offset, v.flags);
824
825 ctx->current_ctx = d;
826
827 v.buf_size = d->buf_size;
828
829 list_add_tail(&d->link, &ctx->context_list);
830
831 PRINT(KERN_INFO, ohci->host->id,
832 "Iso context %d talk on channel %d", d->ctx,
833 v.channel);
834 }
835
836 if (copy_to_user(argp, &v, sizeof(v))) {
837 /* FIXME : free allocated dma resources */
838 return -EFAULT;
839 }
840
841 ohci->ISO_channel_usage |= mask;
842
843 return 0;
844 }
845 case VIDEO1394_IOC_UNLISTEN_CHANNEL:
846 case VIDEO1394_IOC_UNTALK_CHANNEL:
847 {
848 int channel;
849 u64 mask;
850 struct dma_iso_ctx *d;
851
852 if (copy_from_user(&channel, argp, sizeof(int)))
853 return -EFAULT;
854
855 if (channel < 0 || channel >= ISO_CHANNELS) {
856 PRINT(KERN_ERR, ohci->host->id,
857 "Iso channel %d out of bound", channel);
858 return -EINVAL;
859 }
860 mask = (u64)0x1<<channel;
861 if (!(ohci->ISO_channel_usage & mask)) {
862 PRINT(KERN_ERR, ohci->host->id,
863 "Channel %d is not being used", channel);
864 return -ESRCH;
865 }
866
867 /* Mark this channel as unused */
868 ohci->ISO_channel_usage &= ~mask;
869
870 if (cmd == VIDEO1394_IOC_UNLISTEN_CHANNEL)
871 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, channel);
872 else
873 d = find_ctx(&ctx->context_list, OHCI_ISO_TRANSMIT, channel);
874
875 if (d == NULL) return -ESRCH;
876 PRINT(KERN_INFO, ohci->host->id, "Iso context %d "
877 "stop talking on channel %d", d->ctx, channel);
878 free_dma_iso_ctx(d);
879
880 return 0;
881 }
882 case VIDEO1394_IOC_LISTEN_QUEUE_BUFFER:
883 {
884 struct video1394_wait v;
885 struct dma_iso_ctx *d;
886 int next_prg;
887
888 if (copy_from_user(&v, argp, sizeof(v)))
889 return -EFAULT;
890
891 d = find_ctx(&ctx->context_list, OHCI_ISO_RECEIVE, v.channel);
892 if (d == NULL) return -EFAULT;
893
894 if ((v.buffer<0) || (v.buffer>=d->num_desc - 1)) {
895