1 #ifndef _IDE_TIMING_H
2 #define _IDE_TIMING_H
3
4 /*
5 * $Id: ide-timing.h,v 1.6 2001/12/23 22:47:56 vojtech Exp $
6 *
7 * Copyright (c) 1999-2001 Vojtech Pavlik
8 */
9
10 /*
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 * Should you need to contact me, the author, you can do so either by
26 * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail:
27 * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic
28 */
29
30 #include <linux/kernel.h>
31 #include <linux/hdreg.h>
32
33 #define XFER_PIO_5 0x0d
34 #define XFER_UDMA_SLOW 0x4f
35
36 struct ide_timing {
37 short mode;
38 short setup; /* t1 */
39 short act8b; /* t2 for 8-bit io */
40 short rec8b; /* t2i for 8-bit io */
41 short cyc8b; /* t0 for 8-bit io */
42 short active; /* t2 or tD */
43 short recover; /* t2i or tK */
44 short cycle; /* t0 */
45 short udma; /* t2CYCTYP/2 */
46 };
47
48 /*
49 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
50 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
51 * for PIO 5, which is a nonstandard extension and UDMA6, which
52 * is currently supported only by Maxtor drives.
53 */
54
55 static struct ide_timing ide_timing[] = {
56
57 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
58 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
59 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
60 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
61
62 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
63 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
64 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
65
66 { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 },
67
68 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
69 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
70 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
71
72 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
73 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
74 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
75
76 { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 },
77 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
78 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
79
80 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
81 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
82 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
83
84 { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 },
85
86 { -1 }
87 };
88
89 #define IDE_TIMING_SETUP 0x01
90 #define IDE_TIMING_ACT8B 0x02
91 #define IDE_TIMING_REC8B 0x04
92 #define IDE_TIMING_CYC8B 0x08
93 #define IDE_TIMING_8BIT 0x0e
94 #define IDE_TIMING_ACTIVE 0x10
95 #define IDE_TIMING_RECOVER 0x20
96 #define IDE_TIMING_CYCLE 0x40
97 #define IDE_TIMING_UDMA 0x80
98 #define IDE_TIMING_ALL 0xff
99
100 #define FIT(v,vmin,vmax) max_t(short,min_t(short,v,vmax),vmin)
101 #define ENOUGH(v,unit) (((v)-1)/(unit)+1)
102 #define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
103
104 #define XFER_MODE 0xf0
105 #define XFER_UDMA_133 0x48
106 #define XFER_UDMA_100 0x44
107 #define XFER_UDMA_66 0x42
108 #define XFER_UDMA 0x40
109 #define XFER_MWDMA 0x20
110 #define XFER_SWDMA 0x10
111 #define XFER_EPIO 0x01
112 #define XFER_PIO 0x00
113
114 static short ide_find_best_mode(ide_drive_t *drive, int map)
115 {
116 struct hd_driveid *id = drive->id;
117 short best = 0;
118
119 if (!id)
120 return XFER_PIO_SLOW;
121
122 if ((map & XFER_UDMA) && (id->field_valid & 4)) { /* Want UDMA and UDMA bitmap valid */
123
124 if ((map & XFER_UDMA_133) == XFER_UDMA_133)
125 if ((best = (id->dma_ultra & 0x0040) ? XFER_UDMA_6 : 0)) return best;
126
127 if ((map & XFER_UDMA_100) == XFER_UDMA_100)
128 if ((best = (id->dma_ultra & 0x0020) ? XFER_UDMA_5 : 0)) return best;
129
130 if ((map & XFER_UDMA_66) == XFER_UDMA_66)
131 if ((best = (id->dma_ultra & 0x0010) ? XFER_UDMA_4 :
132 (id->dma_ultra & 0x0008) ? XFER_UDMA_3 : 0)) return best;
133
134 if ((best = (id->dma_ultra & 0x0004) ? XFER_UDMA_2 :
135 (id->dma_ultra & 0x0002) ? XFER_UDMA_1 :
136 (id->dma_ultra & 0x0001) ? XFER_UDMA_0 : 0)) return best;
137 }
138
139 if ((map & XFER_MWDMA) && (id->field_valid & 2)) { /* Want MWDMA and drive has EIDE fields */
140
141 if ((best = (id->dma_mword & 0x0004) ? XFER_MW_DMA_2 :
142 (id->dma_mword & 0x0002) ? XFER_MW_DMA_1 :
143 (id->dma_mword & 0x0001) ? XFER_MW_DMA_0 : 0)) return best;
144 }
145
146 if (map & XFER_SWDMA) { /* Want SWDMA */
147
148 if (id->field_valid & 2) { /* EIDE SWDMA */
149
150 if ((best = (id->dma_1word & 0x0004) ? XFER_SW_DMA_2 :
151 (id->dma_1word & 0x0002) ? XFER_SW_DMA_1 :
152 (id->dma_1word & 0x0001) ? XFER_SW_DMA_0 : 0)) return best;
153 }
154
155 if (id->capability & 1) { /* Pre-EIDE style SWDMA */
156
157 if ((best = (id->tDMA == 2) ? XFER_SW_DMA_2 :
158 (id->tDMA == 1) ? XFER_SW_DMA_1 :
159 (id->tDMA == 0) ? XFER_SW_DMA_0 : 0)) return best;
160 }
161 }
162
163
164 if ((map & XFER_EPIO) && (id->field_valid & 2)) { /* EIDE PIO modes */
165
166 if ((best = (drive->id->eide_pio_modes & 4) ? XFER_PIO_5 :
167 (drive->id->eide_pio_modes & 2) ? XFER_PIO_4 :
168 (drive->id->eide_pio_modes & 1) ? XFER_PIO_3 : 0)) return best;
169 }
170
171 return (drive->id->tPIO == 2) ? XFER_PIO_2 :
172 (drive->id->tPIO == 1) ? XFER_PIO_1 :
173 (drive->id->tPIO == 0) ? XFER_PIO_0 : XFER_PIO_SLOW;
174 }
175
176 static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, int T, int UT)
177 {
178 q->setup = EZ(t->setup * 1000, T);
179 q->act8b = EZ(t->act8b * 1000, T);
180 q->rec8b = EZ(t->rec8b * 1000, T);
181 q->cyc8b = EZ(t->cyc8b * 1000, T);
182 q->active = EZ(t->active * 1000, T);
183 q->recover = EZ(t->recover * 1000, T);
184 q->cycle = EZ(t->cycle * 1000, T);
185 q->udma = EZ(t->udma * 1000, UT);
186 }
187
188 static void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, struct ide_timing *m, unsigned int what)
189 {
190 if (what & IDE_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
191 if (what & IDE_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
192 if (what & IDE_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
193 if (what & IDE_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
194 if (what & IDE_TIMING_ACTIVE ) m->active = max(a->active, b->active);
195 if (what & IDE_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
196 if (what & IDE_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
197 if (what & IDE_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
198 }
199
200 static struct ide_timing* ide_timing_find_mode(short speed)
201 {
202 struct ide_timing *t;
203
204 for (t = ide_timing; t->mode != speed; t++)
205 if (t->mode < 0)
206 return NULL;
207 return t;
208 }
209
210 static int ide_timing_compute(ide_drive_t *drive, short speed, struct ide_timing *t, int T, int UT)
211 {
212 struct hd_driveid *id = drive->id;
213 struct ide_timing *s, p;
214
215 /*
216 * Find the mode.
217 */
218
219 if (!(s = ide_timing_find_mode(speed)))
220 return -EINVAL;
221
222 /*
223 * If the drive is an EIDE drive, it can tell us it needs extended
224 * PIO/MWDMA cycle timing.
225 */
226
227 if (id && id->field_valid & 2) { /* EIDE drive */
228
229 memset(&p, 0, sizeof(p));
230
231 switch (speed & XFER_MODE) {
232
233 case XFER_PIO:
234 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = id->eide_pio;
235 else p.cycle = p.cyc8b = id->eide_pio_iordy;
236 break;
237
238 case XFER_MWDMA:
239 p.cycle = id->eide_dma_min;
240 break;
241 }
242
243 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B);
244 }
245
246 /*
247 * Convert the timing to bus clock counts.
248 */
249
250 ide_timing_quantize(s, t, T, UT);
251
252 /*
253 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
254 * and some other commands. We have to ensure that the DMA cycle timing is
255 * slower/equal than the fastest PIO timing.
256 */
257
258 if ((speed & XFER_MODE) != XFER_PIO) {
259 ide_timing_compute(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO), &p, T, UT);
260 ide_timing_merge(&p, t, t, IDE_TIMING_ALL);
261 }
262
263 /*
264 * Lenghten active & recovery time so that cycle time is correct.
265 */
266
267 if (t->act8b + t->rec8b < t->cyc8b) {
268 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
269 t->rec8b = t->cyc8b - t->act8b;
270 }
271
272 if (t->active + t->recover < t->cycle) {
273 t->active += (t->cycle - (t->active + t->recover)) / 2;
274 t->recover = t->cycle - t->active;
275 }
276
277 return 0;
278 }
279
280 #endif
281
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