1 Linux Kernel Makefiles
2
3 This document describes the Linux kernel Makefiles.
4
5 === Table of Contents
6
7 === 1 Overview
8 === 2 Who does what
9 === 3 The kbuild files
10 --- 3.1 Goal definitions
11 --- 3.2 Built-in object goals - obj-y
12 --- 3.3 Loadable module goals - obj-m
13 --- 3.4 Objects which export symbols
14 --- 3.5 Library file goals - lib-y
15 --- 3.6 Descending down in directories
16 --- 3.7 Compilation flags
17 --- 3.8 Command line dependency
18 --- 3.9 Dependency tracking
19 --- 3.10 Special Rules
20 --- 3.11 $(CC) support functions
21
22 === 4 Host Program support
23 --- 4.1 Simple Host Program
24 --- 4.2 Composite Host Programs
25 --- 4.3 Defining shared libraries
26 --- 4.4 Using C++ for host programs
27 --- 4.5 Controlling compiler options for host programs
28 --- 4.6 When host programs are actually built
29 --- 4.7 Using hostprogs-$(CONFIG_FOO)
30
31 === 5 Kbuild clean infrastructure
32
33 === 6 Architecture Makefiles
34 --- 6.1 Set variables to tweak the build to the architecture
35 --- 6.2 Add prerequisites to archprepare:
36 --- 6.3 List directories to visit when descending
37 --- 6.4 Architecture specific boot images
38 --- 6.5 Building non-kbuild targets
39 --- 6.6 Commands useful for building a boot image
40 --- 6.7 Custom kbuild commands
41 --- 6.8 Preprocessing linker scripts
42
43 === 7 Kbuild Variables
44 === 8 Makefile language
45 === 9 Credits
46 === 10 TODO
47
48 === 1 Overview
49
50 The Makefiles have five parts:
51
52 Makefile the top Makefile.
53 .config the kernel configuration file.
54 arch/$(ARCH)/Makefile the arch Makefile.
55 scripts/Makefile.* common rules etc. for all kbuild Makefiles.
56 kbuild Makefiles there are about 500 of these.
57
58 The top Makefile reads the .config file, which comes from the kernel
59 configuration process.
60
61 The top Makefile is responsible for building two major products: vmlinux
62 (the resident kernel image) and modules (any module files).
63 It builds these goals by recursively descending into the subdirectories of
64 the kernel source tree.
65 The list of subdirectories which are visited depends upon the kernel
66 configuration. The top Makefile textually includes an arch Makefile
67 with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
68 architecture-specific information to the top Makefile.
69
70 Each subdirectory has a kbuild Makefile which carries out the commands
71 passed down from above. The kbuild Makefile uses information from the
72 .config file to construct various file lists used by kbuild to build
73 any built-in or modular targets.
74
75 scripts/Makefile.* contains all the definitions/rules etc. that
76 are used to build the kernel based on the kbuild makefiles.
77
78
79 === 2 Who does what
80
81 People have four different relationships with the kernel Makefiles.
82
83 *Users* are people who build kernels. These people type commands such as
84 "make menuconfig" or "make". They usually do not read or edit
85 any kernel Makefiles (or any other source files).
86
87 *Normal developers* are people who work on features such as device
88 drivers, file systems, and network protocols. These people need to
89 maintain the kbuild Makefiles for the subsystem that they are
90 working on. In order to do this effectively, they need some overall
91 knowledge about the kernel Makefiles, plus detailed knowledge about the
92 public interface for kbuild.
93
94 *Arch developers* are people who work on an entire architecture, such
95 as sparc or ia64. Arch developers need to know about the arch Makefile
96 as well as kbuild Makefiles.
97
98 *Kbuild developers* are people who work on the kernel build system itself.
99 These people need to know about all aspects of the kernel Makefiles.
100
101 This document is aimed towards normal developers and arch developers.
102
103
104 === 3 The kbuild files
105
106 Most Makefiles within the kernel are kbuild Makefiles that use the
107 kbuild infrastructure. This chapter introduce the syntax used in the
108 kbuild makefiles.
109 The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
110 be used and if both a 'Makefile' and a 'Kbuild' file exists then the 'Kbuild'
111 file will be used.
112
113 Section 3.1 "Goal definitions" is a quick intro, further chapters provide
114 more details, with real examples.
115
116 --- 3.1 Goal definitions
117
118 Goal definitions are the main part (heart) of the kbuild Makefile.
119 These lines define the files to be built, any special compilation
120 options, and any subdirectories to be entered recursively.
121
122 The most simple kbuild makefile contains one line:
123
124 Example:
125 obj-y += foo.o
126
127 This tell kbuild that there is one object in that directory named
128 foo.o. foo.o will be built from foo.c or foo.S.
129
130 If foo.o shall be built as a module, the variable obj-m is used.
131 Therefore the following pattern is often used:
132
133 Example:
134 obj-$(CONFIG_FOO) += foo.o
135
136 $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
137 If CONFIG_FOO is neither y nor m, then the file will not be compiled
138 nor linked.
139
140 --- 3.2 Built-in object goals - obj-y
141
142 The kbuild Makefile specifies object files for vmlinux
143 in the lists $(obj-y). These lists depend on the kernel
144 configuration.
145
146 Kbuild compiles all the $(obj-y) files. It then calls
147 "$(LD) -r" to merge these files into one built-in.o file.
148 built-in.o is later linked into vmlinux by the parent Makefile.
149
150 The order of files in $(obj-y) is significant. Duplicates in
151 the lists are allowed: the first instance will be linked into
152 built-in.o and succeeding instances will be ignored.
153
154 Link order is significant, because certain functions
155 (module_init() / __initcall) will be called during boot in the
156 order they appear. So keep in mind that changing the link
157 order may e.g. change the order in which your SCSI
158 controllers are detected, and thus you disks are renumbered.
159
160 Example:
161 #drivers/isdn/i4l/Makefile
162 # Makefile for the kernel ISDN subsystem and device drivers.
163 # Each configuration option enables a list of files.
164 obj-$(CONFIG_ISDN) += isdn.o
165 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
166
167 --- 3.3 Loadable module goals - obj-m
168
169 $(obj-m) specify object files which are built as loadable
170 kernel modules.
171
172 A module may be built from one source file or several source
173 files. In the case of one source file, the kbuild makefile
174 simply adds the file to $(obj-m).
175
176 Example:
177 #drivers/isdn/i4l/Makefile
178 obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
179
180 Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
181
182 If a kernel module is built from several source files, you specify
183 that you want to build a module in the same way as above.
184
185 Kbuild needs to know which the parts that you want to build your
186 module from, so you have to tell it by setting an
187 $(<module_name>-objs) variable.
188
189 Example:
190 #drivers/isdn/i4l/Makefile
191 obj-$(CONFIG_ISDN) += isdn.o
192 isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
193
194 In this example, the module name will be isdn.o. Kbuild will
195 compile the objects listed in $(isdn-objs) and then run
196 "$(LD) -r" on the list of these files to generate isdn.o.
197
198 Kbuild recognises objects used for composite objects by the suffix
199 -objs, and the suffix -y. This allows the Makefiles to use
200 the value of a CONFIG_ symbol to determine if an object is part
201 of a composite object.
202
203 Example:
204 #fs/ext2/Makefile
205 obj-$(CONFIG_EXT2_FS) += ext2.o
206 ext2-y := balloc.o bitmap.o
207 ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
208
209 In this example xattr.o is only part of the composite object
210 ext2.o, if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
211
212 Note: Of course, when you are building objects into the kernel,
213 the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
214 kbuild will build an ext2.o file for you out of the individual
215 parts and then link this into built-in.o, as you would expect.
216
217 --- 3.4 Objects which export symbols
218
219 No special notation is required in the makefiles for
220 modules exporting symbols.
221
222 --- 3.5 Library file goals - lib-y
223
224 Objects listed with obj-* are used for modules or
225 combined in a built-in.o for that specific directory.
226 There is also the possibility to list objects that will
227 be included in a library, lib.a.
228 All objects listed with lib-y are combined in a single
229 library for that directory.
230 Objects that are listed in obj-y and additional listed in
231 lib-y will not be included in the library, since they will anyway
232 be accessible.
233 For consistency objects listed in lib-m will be included in lib.a.
234
235 Note that the same kbuild makefile may list files to be built-in
236 and to be part of a library. Therefore the same directory
237 may contain both a built-in.o and a lib.a file.
238
239 Example:
240 #arch/i386/lib/Makefile
241 lib-y := checksum.o delay.o
242
243 This will create a library lib.a based on checksum.o and delay.o.
244 For kbuild to actually recognize that there is a lib.a being build
245 the directory shall be listed in libs-y.
246 See also "6.3 List directories to visit when descending".
247
248 Usage of lib-y is normally restricted to lib/ and arch/*/lib.
249
250 --- 3.6 Descending down in directories
251
252 A Makefile is only responsible for building objects in its own
253 directory. Files in subdirectories should be taken care of by
254 Makefiles in these subdirs. The build system will automatically
255 invoke make recursively in subdirectories, provided you let it know of
256 them.
257
258 To do so obj-y and obj-m are used.
259 ext2 lives in a separate directory, and the Makefile present in fs/
260 tells kbuild to descend down using the following assignment.
261
262 Example:
263 #fs/Makefile
264 obj-$(CONFIG_EXT2_FS) += ext2/
265
266 If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
267 the corresponding obj- variable will be set, and kbuild will descend
268 down in the ext2 directory.
269 Kbuild only uses this information to decide that it needs to visit
270 the directory, it is the Makefile in the subdirectory that
271 specifies what is modules and what is built-in.
272
273 It is good practice to use a CONFIG_ variable when assigning directory
274 names. This allows kbuild to totally skip the directory if the
275 corresponding CONFIG_ option is neither 'y' nor 'm'.
276
277 --- 3.7 Compilation flags
278
279 EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS
280
281 All the EXTRA_ variables apply only to the kbuild makefile
282 where they are assigned. The EXTRA_ variables apply to all
283 commands executed in the kbuild makefile.
284
285 $(EXTRA_CFLAGS) specifies options for compiling C files with
286 $(CC).
287
288 Example:
289 # drivers/sound/emu10k1/Makefile
290 EXTRA_CFLAGS += -I$(obj)
291 ifdef DEBUG
292 EXTRA_CFLAGS += -DEMU10K1_DEBUG
293 endif
294
295
296 This variable is necessary because the top Makefile owns the
297 variable $(CFLAGS) and uses it for compilation flags for the
298 entire tree.
299
300 $(EXTRA_AFLAGS) is a similar string for per-directory options
301 when compiling assembly language source.
302
303 Example:
304 #arch/x86_64/kernel/Makefile
305 EXTRA_AFLAGS := -traditional
306
307
308 $(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
309 per-directory options to $(LD) and $(AR).
310
311 Example:
312 #arch/m68k/fpsp040/Makefile
313 EXTRA_LDFLAGS := -x
314
315 CFLAGS_$@, AFLAGS_$@
316
317 CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
318 kbuild makefile.
319
320 $(CFLAGS_$@) specifies per-file options for $(CC). The $@
321 part has a literal value which specifies the file that it is for.
322
323 Example:
324 # drivers/scsi/Makefile
325 CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
326 CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
327 -DGDTH_STATISTICS
328 CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
329
330 These three lines specify compilation flags for aha152x.o,
331 gdth.o, and seagate.o
332
333 $(AFLAGS_$@) is a similar feature for source files in assembly
334 languages.
335
336 Example:
337 # arch/arm/kernel/Makefile
338 AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
339 AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
340
341 --- 3.9 Dependency tracking
342
343 Kbuild tracks dependencies on the following:
344 1) All prerequisite files (both *.c and *.h)
345 2) CONFIG_ options used in all prerequisite files
346 3) Command-line used to compile target
347
348 Thus, if you change an option to $(CC) all affected files will
349 be re-compiled.
350
351 --- 3.10 Special Rules
352
353 Special rules are used when the kbuild infrastructure does
354 not provide the required support. A typical example is
355 header files generated during the build process.
356 Another example is the architecture specific Makefiles which
357 needs special rules to prepare boot images etc.
358
359 Special rules are written as normal Make rules.
360 Kbuild is not executing in the directory where the Makefile is
361 located, so all special rules shall provide a relative
362 path to prerequisite files and target files.
363
364 Two variables are used when defining special rules:
365
366 $(src)
367 $(src) is a relative path which points to the directory
368 where the Makefile is located. Always use $(src) when
369 referring to files located in the src tree.
370
371 $(obj)
372 $(obj) is a relative path which points to the directory
373 where the target is saved. Always use $(obj) when
374 referring to generated files.
375
376 Example:
377 #drivers/scsi/Makefile
378 $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
379 $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
380
381 This is a special rule, following the normal syntax
382 required by make.
383 The target file depends on two prerequisite files. References
384 to the target file are prefixed with $(obj), references
385 to prerequisites are referenced with $(src) (because they are not
386 generated files).
387
388 --- 3.11 $(CC) support functions
389
390 The kernel may be build with several different versions of
391 $(CC), each supporting a unique set of features and options.
392 kbuild provide basic support to check for valid options for $(CC).
393 $(CC) is useally the gcc compiler, but other alternatives are
394 available.
395
396 as-option
397 as-option is used to check if $(CC) when used to compile
398 assembler (*.S) files supports the given option. An optional
399 second option may be specified if first option are not supported.
400
401 Example:
402 #arch/sh/Makefile
403 cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
404
405 In the above example cflags-y will be assinged the the option
406 -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
407 The second argument is optional, and if supplied will be used
408 if first argument is not supported.
409
410 cc-option
411 cc-option is used to check if $(CC) support a given option, and not
412 supported to use an optional second option.
413
414 Example:
415 #arch/i386/Makefile
416 cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
417
418 In the above example cflags-y will be assigned the option
419 -march=pentium-mmx if supported by $(CC), otherwise -march-i586.
420 The second argument to cc-option is optional, and if omitted
421 cflags-y will be assigned no value if first option is not supported.
422
423 cc-option-yn
424 cc-option-yn is used to check if gcc supports a given option
425 and return 'y' if supported, otherwise 'n'.
426
427 Example:
428 #arch/ppc/Makefile
429 biarch := $(call cc-option-yn, -m32)
430 aflags-$(biarch) += -a32
431 cflags-$(biarch) += -m32
432
433 In the above example $(biarch) is set to y if $(CC) supports the -m32
434 option. When $(biarch) equals to y the expanded variables $(aflags-y)
435 and $(cflags-y) will be assigned the values -a32 and -m32.
436
437 cc-option-align
438 gcc version >= 3.0 shifted type of options used to speify
439 alignment of functions, loops etc. $(cc-option-align) whrn used
440 as prefix to the align options will select the right prefix:
441 gcc < 3.00
442 cc-option-align = -malign
443 gcc >= 3.00
444 cc-option-align = -falign
445
446 Example:
447 CFLAGS += $(cc-option-align)-functions=4
448
449 In the above example the option -falign-functions=4 is used for
450 gcc >= 3.00. For gcc < 3.00 -malign-functions=4 is used.
451
452 cc-version
453 cc-version return a numerical version of the $(CC) compiler version.
454 The format is <major><minor> where both are two digits. So for example
455 gcc 3.41 would return 0341.
456 cc-version is useful when a specific $(CC) version is faulty in one
457 area, for example the -mregparm=3 were broken in some gcc version
458 even though the option was accepted by gcc.
459
460 Example:
461 #arch/i386/Makefile
462 cflags-y += $(shell \
463 if [ $(call cc-version) -ge 0300 ] ; then \
464 echo "-mregparm=3"; fi ;)
465
466 In the above example -mregparm=3 is only used for gcc version greater
467 than or equal to gcc 3.0.
468
469 cc-ifversion
470 cc-ifversion test the version of $(CC) and equals last argument if
471 version expression is true.
472
473 Example:
474 #fs/reiserfs/Makefile
475 EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)
476
477 In this example EXTRA_CFLAGS will be assigned the value -O1 if the
478 $(CC) version is less than 4.2.
479 cc-ifversion takes all the shell operators:
480 -eq, -ne, -lt, -le, -gt, and -ge
481 The third parameter may be a text as in this example, but it may also
482 be an expanded variable or a macro.
483
484
485 === 4 Host Program support
486
487 Kbuild supports building executables on the host for use during the
488 compilation stage.
489 Two steps are required in order to use a host executable.
490
491 The first step is to tell kbuild that a host program exists. This is
492 done utilising the variable hostprogs-y.
493
494 The second step is to add an explicit dependency to the executable.
495 This can be done in two ways. Either add the dependency in a rule,
496 or utilise the variable $(always).
497 Both possibilities are described in the following.
498
499 --- 4.1 Simple Host Program
500
501 In some cases there is a need to compile and run a program on the
502 computer where the build is running.
503 The following line tells kbuild that the program bin2hex shall be
504 built on the build host.
505
506 Example:
507 hostprogs-y := bin2hex
508
509 Kbuild assumes in the above example that bin2hex is made from a single
510 c-source file named bin2hex.c located in the same directory as
511 the Makefile.
512
513 --- 4.2 Composite Host Programs
514
515 Host programs can be made up based on composite objects.
516 The syntax used to define composite objects for host programs is
517 similar to the syntax used for kernel objects.
518 $(<executeable>-objs) list all objects used to link the final
519 executable.
520
521 Example:
522 #scripts/lxdialog/Makefile
523 hostprogs-y := lxdialog
524 lxdialog-objs := checklist.o lxdialog.o
525
526 Objects with extension .o are compiled from the corresponding .c
527 files. In the above example checklist.c is compiled to checklist.o
528 and lxdialog.c is compiled to lxdialog.o.
529 Finally the two .o files are linked to the executable, lxdialog.
530 Note: The syntax <executable>-y is not permitted for host-programs.
531
532 --- 4.3 Defining shared libraries
533
534 Objects with extension .so are considered shared libraries, and
535 will be compiled as position independent objects.
536 Kbuild provides support for shared libraries, but the usage
537 shall be restricted.
538 In the following example the libkconfig.so shared library is used
539 to link the executable conf.
540
541 Example:
542 #scripts/kconfig/Makefile
543 hostprogs-y := conf
544 conf-objs := conf.o libkconfig.so
545 libkconfig-objs := expr.o type.o
546
547 Shared libraries always require a corresponding -objs line, and
548 in the example above the shared library libkconfig is composed by
549 the two objects expr.o and type.o.
550 expr.o and type.o will be built as position independent code and
551 linked as a shared library libkconfig.so. C++ is not supported for
552 shared libraries.
553
554 --- 4.4 Using C++ for host programs
555
556 kbuild offers support for host programs written in C++. This was
557 introduced solely to support kconfig, and is not recommended
558 for general use.
559
560 Example:
561 #scripts/kconfig/Makefile
562 hostprogs-y := qconf
563 qconf-cxxobjs := qconf.o
564
565 In the example above the executable is composed of the C++ file
566 qconf.cc - identified by $(qconf-cxxobjs).
567
568 If qconf is composed by a mixture of .c and .cc files, then an
569 additional line can be used to identify this.
570
571 Example:
572 #scripts/kconfig/Makefile
573 hostprogs-y := qconf
574 qconf-cxxobjs := qconf.o
575 qconf-objs := check.o
576
577 --- 4.5 Controlling compiler options for host programs
578
579 When compiling host programs, it is possible to set specific flags.
580 The programs will always be compiled utilising $(HOSTCC) passed
581 the options specified in $(HOSTCFLAGS).
582 To set flags that will take effect for all host programs created
583 in that Makefile use the variable HOST_EXTRACFLAGS.
584
585 Example:
586 #scripts/lxdialog/Makefile
587 HOST_EXTRACFLAGS += -I/usr/include/ncurses
588
589 To set specific flags for a single file the following construction
590 is used:
591
592 Example:
593 #arch/ppc64/boot/Makefile
594 HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
595
596 It is also possible to specify additional options to the linker.
597
598 Example:
599 #scripts/kconfig/Makefile
600 HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
601
602 When linking qconf it will be passed the extra option "-L$(QTDIR)/lib".
603
604 --- 4.6 When host programs are actually built
605
606 Kbuild will only build host-programs when they are referenced
607 as a prerequisite.
608 This is possible in two ways:
609
610 (1) List the prerequisite explicitly in a special rule.
611
612 Example:
613 #drivers/pci/Makefile
614 hostprogs-y := gen-devlist
615 $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
616 ( cd $(obj); ./gen-devlist ) < $<
617
618 The target $(obj)/devlist.h will not be built before
619 $(obj)/gen-devlist is updated. Note that references to
620 the host programs in special rules must be prefixed with $(obj).
621
622 (2) Use $(always)
623 When there is no suitable special rule, and the host program
624 shall be built when a makefile is entered, the $(always)
625 variable shall be used.
626
627 Example:
628 #scripts/lxdialog/Makefile
629 hostprogs-y := lxdialog
630 always := $(hostprogs-y)
631
632 This will tell kbuild to build lxdialog even if not referenced in
633 any rule.
634
635 --- 4.7 Using hostprogs-$(CONFIG_FOO)
636
637 A typcal pattern in a Kbuild file lok like this:
638
639 Example:
640 #scripts/Makefile
641 hostprogs-$(CONFIG_KALLSYMS) += kallsyms
642
643 Kbuild knows about both 'y' for built-in and 'm' for module.
644 So if a config symbol evaluate to 'm', kbuild will still build
645 the binary. In other words Kbuild handle hostprogs-m exactly
646 like hostprogs-y. But only hostprogs-y is recommend used
647 when no CONFIG symbol are involved.
648
649 === 5 Kbuild clean infrastructure
650
651 "make clean" deletes most generated files in the src tree where the kernel
652 is compiled. This includes generated files such as host programs.
653 Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
654 $(extra-y) and $(targets). They are all deleted during "make clean".
655 Files matching the patterns "*.[oas]", "*.ko", plus some additional files
656 generated by kbuild are deleted all over the kernel src tree when
657 "make clean" is executed.
658
659 Additional files can be specified in kbuild makefiles by use of $(clean-files).
660
661 Example:
662 #drivers/pci/Makefile
663 clean-files := devlist.h classlist.h
664
665 When executing "make clean", the two files "devlist.h classlist.h" will
666 be deleted. Kbuild will assume files to be in same relative directory as the
667 Makefile except if an absolute path is specified (path starting with '/').
668
669 To delete a directory hirachy use:
670 Example:
671 #scripts/package/Makefile
672 clean-dirs := $(objtree)/debian/
673
674 This will delete the directory debian, including all subdirectories.
675 Kbuild will assume the directories to be in the same relative path as the
676 Makefile if no absolute path is specified (path does not start with '/').
677
678 Usually kbuild descends down in subdirectories due to "obj-* := dir/",
679 but in the architecture makefiles where the kbuild infrastructure
680 is not sufficient this sometimes needs to be explicit.
681
682 Example:
683 #arch/i386/boot/Makefile
684 subdir- := compressed/
685
686 The above assignment instructs kbuild to descend down in the
687 directory compressed/ when "make clean" is executed.
688
689 To support the clean infrastructure in the Makefiles that builds the
690 final bootimage there is an optional target named archclean:
691
692 Example:
693 #arch/i386/Makefile
694 archclean:
695 $(Q)$(MAKE) $(clean)=arch/i386/boot
696
697 When "make clean" is executed, make will descend down in arch/i386/boot,
698 and clean as usual. The Makefile located in arch/i386/boot/ may use
699 the subdir- trick to descend further down.
700
701 Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
702 included in the top level makefile, and the kbuild infrastructure
703 is not operational at that point.
704
705 Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
706 be visited during "make clean".
707
708 === 6 Architecture Makefiles
709
710 The top level Makefile sets up the environment and does the preparation,
711 before starting to descend down in the individual directories.
712 The top level makefile contains the generic part, whereas the
713 arch/$(ARCH)/Makefile contains what is required to set-up kbuild
714 to the said architecture.
715 To do so arch/$(ARCH)/Makefile sets a number of variables, and defines
716 a few targets.
717
718 When kbuild executes the following steps are followed (roughly):
719 1) Configuration of the kernel => produced .config
720 2) Store kernel version in include/linux/version.h
721 3) Symlink include/asm to include/asm-$(ARCH)
722 4) Updating all other prerequisites to the target prepare:
723 - Additional prerequisites are specified in arch/$(ARCH)/Makefile
724 5) Recursively descend down in all directories listed in
725 init-* core* drivers-* net-* libs-* and build all targets.
726 - The value of the above variables are extended in arch/$(ARCH)/Makefile.
727 6) All object files are then linked and the resulting file vmlinux is
728 located at the root of the src tree.
729 The very first objects linked are listed in head-y, assigned by
730 arch/$(ARCH)/Makefile.
731 7) Finally the architecture specific part does any required post processing
732 and builds the final bootimage.
733 - This includes building boot records
734 - Preparing initrd images and the like
735
736
737 --- 6.1 Set variables to tweak the build to the architecture
738
739 LDFLAGS Generic $(LD) options
740
741 Flags used for all invocations of the linker.
742 Often specifying the emulation is sufficient.
743
744 Example:
745 #arch/s390/Makefile
746 LDFLAGS := -m elf_s390
747 Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
748 the flags used. See chapter 7.
749
750 LDFLAGS_MODULE Options for $(LD) when linking modules
751
752 LDFLAGS_MODULE is used to set specific flags for $(LD) when
753 linking the .ko files used for modules.
754 Default is "-r", for relocatable output.
755
756 LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
757
758 LDFLAGS_vmlinux is used to specify additional flags to pass to
759 the linker when linking the final vmlinux.
760 LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
761
762 Example:
763 #arch/i386/Makefile
764 LDFLAGS_vmlinux := -e stext
765
766 OBJCOPYFLAGS objcopy flags
767
768 When $(call if_changed,objcopy) is used to translate a .o file,
769 then the flags specified in OBJCOPYFLAGS will be used.
770 $(call if_changed,objcopy) is often used to generate raw binaries on
771 vmlinux.
772
773 Example:
774 #arch/s390/Makefile
775 OBJCOPYFLAGS := -O binary
776
777 #arch/s390/boot/Makefile
778 $(obj)/image: vmlinux FORCE
779 $(call if_changed,objcopy)
780
781 In this example the binary $(obj)/image is a binary version of
782 vmlinux. The usage of $(call if_changed,xxx) will be described later.
783
784 AFLAGS $(AS) assembler flags
785
786 Default value - see top level Makefile
787 Append or modify as required per architecture.
788
789 Example:
790 #arch/sparc64/Makefile
791 AFLAGS += -m64 -mcpu=ultrasparc
792
793 CFLAGS $(CC) compiler flags
794
795 Default value - see top level Makefile
796 Append or modify as required per architecture.
797
798 Often the CFLAGS variable depends on the configuration.
799
800 Example:
801 #arch/i386/Makefile
802 cflags-$(CONFIG_M386) += -march=i386
803 CFLAGS += $(cflags-y)
804
805 Many arch Makefiles dynamically run the target C compiler to
806 probe supported options:
807
808 #arch/i386/Makefile
809
810 ...
811 cflags-$(CONFIG_MPENTIUMII) += $(call cc-option,\
812 -march=pentium2,-march=i686)
813 ...
814 # Disable unit-at-a-time mode ...
815 CFLAGS += $(call cc-option,-fno-unit-at-a-time)
816 ...
817
818
819 The first examples utilises the trick that a config option expands
820 to 'y' when selected.
821
822 CFLAGS_KERNEL $(CC) options specific for built-in
823
824 $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
825 resident kernel code.
826
827 CFLAGS_MODULE $(CC) options specific for modules
828
829 $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
830 for loadable kernel modules.
831
832
833 --- 6.2 Add prerequisites to archprepare:
834
835 The archprepare: rule is used to list prerequisites that needs to be
836 built before starting to descend down in the subdirectories.
837 This is usual header files containing assembler constants.
838
839 Example:
840 #arch/arm/Makefile
841 archprepare: maketools
842
843 In this example the file target maketools will be processed
844 before descending down in the subdirectories.
845 See also chapter XXX-TODO that describe how kbuild supports
846 generating offset header files.
847
848
849 --- 6.3 List directories to visit when descending
850
851 An arch Makefile cooperates with the top Makefile to define variables
852 which specify how to build the vmlinux file. Note that there is no
853 corresponding arch-specific section for modules; the module-building
854 machinery is all architecture-independent.
855
856
857 head-y, init-y, core-y, libs-y, drivers-y, net-y
858
859 $(head-y) list objects to be linked first in vmlinux.
860 $(libs-y) list directories where a lib.a archive can be located.
861 The rest list directories where a built-in.o object file can be located.
862
863 $(init-y) objects will be located after $(head-y).
864 Then the rest follows in this order:
865 $(core-y), $(libs-y), $(drivers-y) and $(net-y).
866
867 The top level Makefile define values for all generic directories,
868 and arch/$(ARCH)/Makefile only adds architecture specific directories.
869
870 Example:
871 #arch/sparc64/Makefile
872 core-y += arch/sparc64/kernel/
873 libs-y += arch/sparc64/prom/ arch/sparc64/lib/
874 drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
875
876
877 --- 6.4 Architecture specific boot images
878
879 An arch Makefile specifies goals that take the vmlinux file, compress
880 it, wrap it in bootstrapping code, and copy the resulting files
881 somewhere. This includes various kinds of installation commands.
882 The actual goals are not standardized across architectures.
883
884 It is common to locate any additional processing in a boot/
885 directory below arch/$(ARCH)/.
886
887 Kbuild does not provide any smart way to support building a
888 target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
889 call make manually to build a target in boot/.
890
891 The recommended approach is to include shortcuts in
892 arch/$(ARCH)/Makefile, and use the full path when calling down
893 into the arch/$(ARCH)/boot/Makefile.
894
895 Example:
896 #arch/i386/Makefile
897 boot := arch/i386/boot
898 bzImage: vmlinux
899 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
900
901 "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
902 make in a subdirectory.
903
904 There are no rules for naming of the architecture specific targets,
905 but executing "make help" will list all relevant targets.
906 To support this $(archhelp) must be defined.
907
908 Example:
909 #arch/i386/Makefile
910 define archhelp
911 echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
912 endef
913
914 When make is executed without arguments, the first goal encountered
915 will be built. In the top level Makefile the first goal present
916 is all:.
917 An architecture shall always per default build a bootable image.
918 In "make help" the default goal is highlighted with a '*'.
919 Add a new prerequisite to all: to select a default goal different
920 from vmlinux.
921
922 Example:
923 #arch/i386/Makefile
924 all: bzImage
925
926 When "make" is executed without arguments, bzImage will be built.
927
928 --- 6.5 Building non-kbuild targets
929
930 extra-y
931
932 extra-y specify additional targets created in the current
933 directory, in addition to any targets specified by obj-*.
934
935 Listing all targets in extra-y is required for two purposes:
936 1) Enable kbuild to check changes in command lines
937 - When $(call if_changed,xxx) is used
938 2) kbuild knows what files to delete during "make clean"
939
940 Example:
941 #arch/i386/kernel/Makefile
942 extra-y := head.o init_task.o
943
944 In this example extra-y is used to list object files that
945 shall be built, but shall not be linked as part of built-in.o.
946
947
948 --- 6.6 Commands useful for building a boot image
949
950 Kbuild provides a few macros that are useful when building a
951 boot image.
952
953 if_changed
954
955 if_changed is the infrastructure used for the following commands.
956
957 Usage:
958 target: source(s) FORCE
959 $(call if_changed,ld/objcopy/gzip)
960
961 When the rule is evaluated it is checked to see if any files
962 needs an update, or the commandline has changed since last
963 invocation. The latter will force a rebuild if any options
964 to the executable have changed.
965 Any target that utilises if_changed must be listed in $(targets),
966 otherwise the command line check will fail, and the target will
967 always be built.
968 Assignments to $(targets) are without $(obj)/ prefix.
969 if_changed may be used in conjunction with custom commands as
970 defined in 6.7 "Custom kbuild commands".
971
972 Note: It is a typical mistake to forget the FORCE prerequisite.
973 Another common pitfall is that whitespace is sometimes
974 significant; for instance, the below will fail (note the extra space
975 after the comma):
976 target: source(s) FORCE
977 #WRONG!# $(call if_changed, ld/objcopy/gzip)
978
979 ld
980 Link target. Often LDFLAGS_$@ is used to set specific options to ld.
981
982 objcopy
983 Copy binary. Uses OBJCOPYFLAGS usually specified in
984 arch/$(ARCH)/Makefile.
985 OBJCOPYFLAGS_$@ may be used to set additional options.
986
987 gzip
988 Compress target. Use maximum compression to compress target.
989
990 Example:
991 #arch/i386/boot/Makefile
992 LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
993 LDFLAGS_setup := -Ttext 0x0 -s --oformat binary -e begtext
994
995 targets += setup setup.o bootsect bootsect.o
996 $(obj)/setup $(obj)/bootsect: %: %.o FORCE
997 $(call if_changed,ld)
998
999 In this example there are two possible targets, requiring different
1000 options to the linker. the linker options are specified using the
1001 LDFLAGS_$@ syntax - one for each potential target.
1002 $(targets) are assinged all potential targets, herby kbuild knows
1003 the targets and will:
1004 1) check for commandline changes
1005 2) delete target during make clean
1006
1007 The ": %: %.o" part of the prerequisite is a shorthand that
1008 free us from listing the setup.o and bootsect.o files.
1009 Note: It is a common mistake to forget the "target :=" assignment,
1010 resulting in the target file being recompiled for no
1011 obvious reason.
1012
1013
1014 --- 6.7 Custom kbuild commands
1015
1016 When kbuild is executing with KBUILD_VERBOSE=0 then only a shorthand
1017 of a command is normally displayed.
1018 To enable this behaviour for custom commands kbuild requires
1019 two variables to be set:
1020 quiet_cmd_<command> - what shall be echoed
1021 cmd_<command> - the command to execute
1022
1023 Example:
1024 #
1025 quiet_cmd_image = BUILD $@
1026 cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
1027 $(obj)/vmlinux.bin > $@
1028
1029 targets += bzImage
1030 $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
1031 $(call if_changed,image)
1032 @echo 'Kernel: $@ is ready'
1033
1034 When updating the $(obj)/bzImage target the line:
1035
1036 BUILD arch/i386/boot/bzImage
1037
1038 will be displayed with "make KBUILD_VERBOSE=0".
1039
1040
1041 --- 6.8 Preprocessing linker scripts
1042
1043 When the vmlinux image is build the linker script:
1044 arch/$(ARCH)/kernel/vmlinux.lds is used.
1045 The script is a preprocessed variant of the file vmlinux.lds.S
1046 located in the same directory.
1047 kbuild knows .lds file and includes a rule *lds.S -> *lds.
1048
1049 Example:
1050 #arch/i386/kernel/Makefile
1051 always := vmlinux.lds
1052
1053 #Makefile
1054 export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
1055
1056 The assigment to $(always) is used to tell kbuild to build the
1057 target: vmlinux.lds.
1058 The assignment to $(CPPFLAGS_vmlinux.lds) tell kbuild to use the
1059 specified options when building the target vmlinux.lds.
1060
1061 When building the *.lds target kbuild used the variakles:
1062 CPPFLAGS : Set in top-level Makefile
1063 EXTRA_CPPFLAGS : May be set in the kbuild makefile
1064 CPPFLAGS_$(@F) : Target specific flags.
1065 Note that the full filename is used in this
1066 assignment.
1067
1068 The kbuild infrastructure for *lds file are used in several
1069 architecture specific files.
1070
1071
1072 === 7 Kbuild Variables
1073
1074 The top Makefile exports the following variables:
1075
1076 VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
1077
1078 These variables define the current kernel version. A few arch
1079 Makefiles actually use these values directly; they should use
1080 $(KERNELRELEASE) instead.
1081
1082 $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
1083 three-part version number, such as "2", "4", and "0". These three
1084 values are always numeric.
1085
1086 $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
1087 or additional patches. It is usually some non-numeric string
1088 such as "-pre4", and is often blank.
1089
1090 KERNELRELEASE
1091
1092 $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
1093 for constructing installation directory names or showing in
1094 version strings. Some arch Makefiles use it for this purpose.
1095
1096 ARCH
1097
1098 This variable defines the target architecture, such as "i386",
1099 "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
1100 determine which files to compile.
1101
1102 By default, the top Makefile sets $(ARCH) to be the same as the
1103 host system architecture. For a cross build, a user may
1104 override the value of $(ARCH) on the command line:
1105
1106 make ARCH=m68k ...
1107
1108
1109 INSTALL_PATH
1110
1111 This variable defines a place for the arch Makefiles to install
1112 the resident kernel image and System.map file.
1113 Use this for architecture specific install targets.
1114
1115 INSTALL_MOD_PATH, MODLIB
1116
1117 $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
1118 installation. This variable is not defined in the Makefile but
1119 may be passed in by the user if desired.
1120
1121 $(MODLIB) specifies the directory for module installation.
1122 The top Makefile defines $(MODLIB) to
1123 $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
1124 override this value on the command line if desired.
1125
1126 === 8 Makefile language
1127
1128 The kernel Makefiles are designed to run with GNU Make. The Makefiles
1129 use only the documented features of GNU Make, but they do use many
1130 GNU extensions.
1131
1132 GNU Make supports elementary list-processing functions. The kernel
1133 Makefiles use a novel style of list building and manipulation with few
1134 "if" statements.
1135
1136 GNU Make has two assignment operators, ":=" and "=". ":=" performs
1137 immediate evaluation of the right-hand side and stores an actual string
1138 into the left-hand side. "=" is like a formula definition; it stores the
1139 right-hand side in an unevaluated form and then evaluates this form each
1140 time the left-hand side is used.
1141
1142 There are some cases where "=" is appropriate. Usually, though, ":="
1143 is the right choice.
1144
1145 === 9 Credits
1146
1147 Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
1148 Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
1149 Updates by Sam Ravnborg <sam@ravnborg.org>
1150
1151 === 10 TODO
1152
1153 - Describe how kbuild support shipped files with _shipped.
1154 - Generating offset header files.
1155 - Add more variables to section 7?
1156
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