Re: Ordering between PCI config space writes and MMIO reads?

From: John Partridge <johnip_at_sgi.com>
Date: 2006-11-02 03:27:19
Roland Dreier wrote:
>  > I'm beginning to think Michael Tsirkin has the only solution to this
>  > -- architectures need to check that their hardware blocks until the
>  > config write completion has occurred (and if not, simulate that it has
>  > in software).
> 
> OK, I guess I'm convinced.  The vague language in the base PCI 3.0
> spec about "dependencies" made me think that a read of a config
> register had to wait until all previous writes to the same register
> are done.  So I'll drop this patch for now.
> 
> John, you'll need to try and come up with a way to solve this in the
> Altix implementation of pci_write_config_xxx().
> 
>  - R.

Sorry, but I find this change a bit puzzling. The problem is particular to
the PPB on the HCA and not Altix. I can't see anywhere that a PCI Config Write
is required to block until completion, it is the driver and the HCA ,not the
Altix hardware that requires the Config Write to have completed before we
leave mthca_reset() Changing pci_write_config_xxx() will change the behavior
for ALL drivers and the possibility of breaking something else. The fix was
very low risk in mthca_reset(), changing the PCI code to fix this is much
more onerous.

I know you must feel like "piggy in the middle" with this, so I don't mean
to cause you any problems, but I guess I don't understand the reluctance for
the driver fix.

John

-- 
John Partridge

Silicon Graphics Inc
Tel:	651-683-3428
Vnet:	233-3428
E-Mail:	johnip@sgi.com
-
To unsubscribe from this list: send the line "unsubscribe linux-ia64" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Received on Thu Nov 02 03:30:02 2006

This archive was generated by hypermail 2.1.8 : 2006-11-02 03:30:16 EST