Re: Ordering between PCI config space writes and MMIO reads?

From: Michael S. Tsirkin <mst_at_mellanox.co.il>
Date: 2006-11-01 07:28:00
Quoting r. Roland Dreier <rdreier@cisco.com>:
> Subject: Re: Ordering between PCI config space writes and MMIO reads?
> 
>  > Here's what I don't understand: according to PCI rules, pci config read
>  > can bypass pci config write (both are non-posted).
>  > So why does doing it help flush the writes as the comment claims?
> 
> No, I don't believe a read of a config register can pass a write of
> the same register.  (Someone correct me if I'm wrong)

It can if PCI-X/PCI-Ex spec is anything to go by.

For example, see table 2-23, transaction ordering rules, in the PCI-express
spec: it is marked as "Y/N: there are no requirements.  The second transaction
may optionally pass the first transaction or be blocked by it."

In typical systems the OS should take care not to start a new
non-posted transaction before the previous one completed.
In particular, all intel and ppc systems I've seen simply block the CPU
unti the split completion arrives.

I find it hard to believe that Altix des not supply a way to check
that completion for config write transaction has arrived.


-- 
MST
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Received on Wed Nov 01 07:28:53 2006

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