Re: Ordering between PCI config space writes and MMIO reads?

From: Roland Dreier <rdreier_at_cisco.com>
Date: 2006-10-26 00:11:06
 > I'm looking at arch/ia64/pci/pci.c.
 > Wouldn't it be reasonable to include memory barriers around calls
 > to SAL config space access functions?

It's reasonable, but is there a memory barrier strong enough to
guarantee that a config write has actually completed?

 - R.
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Received on Thu Oct 26 00:11:27 2006

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