Re: Ordering between PCI config space writes and MMIO reads?

From: Roland Dreier <rdreier_at_cisco.com>
Date: 2006-10-25 07:29:47
 > It is good to be conservative in this area. Some AMD chipsets at least
 > had ordering problems with some configurations in the K7 era.

Could you expand a little?  Do you mean that the arch implementation
of pci_write_config_xxx() should have extra barriers, or that drivers
should do belt-and-suspenders flushes to make sure config writes are
really done properly?

 - R.
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Received on Wed Oct 25 07:30:19 2006

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