Re: Patch [2/2] relax per-cpu TLB requirement to DTC

From: Christoph Lameter <clameter_at_sgi.com>
Date: 2006-10-14 04:54:22
On Fri, 13 Oct 2006, Chen, Kenneth W wrote:

> -	andcm r18=0x10,r18	// bit 4=~address-bit(61)
> +(p10)	sub r19=r19,r26
> +(p10)	mov cr.itir=r25
>  	cmp.ne p8,p0=r0,r23

This look somewhat familiar. Any chance that you could merge my mods to 
the alt_dtlb_miss handler? Both have to modify ITIR. 

Also there may be a conflict since we both use high address bits?
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Received on Sat Oct 14 04:54:33 2006

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