RE: Synchronizing Bit operations V2

From: Chen, Kenneth W <kenneth.w.chen_at_intel.com>
Date: 2006-03-31 14:02:00
Christoph Lameter wrote on Thursday, March 30, 2006 6:56 PM
> > By the way, this is the same thing on x86: look at include/asm-i386/bitops.h:
> > 
> > #define smp_mb__before_clear_bit()      barrier()
> > #define smp_mb__after_clear_bit()       barrier()
> > 
> > A simple compiler barrier, nothing but
> > #define barrier() __asm__ __volatile__("": : :"memory")
> > 
> > See, no memory ordering there, because clear_bit already has a LOCK prefix.
> 
> And that implies barrier behavior right?

No, not the memory ordering semantics you are thinking about.  It just tell
compiler not to be over smart and schedule a load operation above that point
Intel compiler is good at schedule memory load way ahead of its use to hide
memory latency. gcc probably does that too, I'm not 100% sure. This prevents
the compiler to schedule load before that line.

- Ken
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Received on Fri Mar 31 14:02:41 2006

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