RE: Synchronizing Bit operations V2

From: Chen, Kenneth W <kenneth.w.chen_at_intel.com>
Date: 2006-03-31 13:45:11
Christoph Lameter wrote on Thursday, March 30, 2006 6:38 PM
> > > Neither one is correct because there will always be one combination of 
> > > clear_bit with these macros that does not generate the required memory 
> > > barrier.
> > 
> > Can you give an example?  Which combination?
> 
> For Option(1)
> 
> smp_mb__before_clear_bit()
> clear_bit(...)(

Sorry, you totally lost me.  It could me I'm extremely slow today.  For
option (1), on ia64, clear_bit has release semantic already.  The comb
of __before_clear_bit + clear_bit provides the required ordering.  Did
I miss something?  By the way, we are talking about detail implementation
on one specific architecture.  Not some generic concept that clear_bit
has no ordering stuff in there.

- Ken
-
To unsubscribe from this list: send the line "unsubscribe linux-ia64" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Received on Fri Mar 31 13:46:19 2006

This archive was generated by hypermail 2.1.8 : 2006-03-31 13:46:28 EST