On Thu, 30 Mar 2006, Chen, Kenneth W wrote: > Christoph Lameter wrote on Thursday, March 30, 2006 4:18 PM > > Note that the current semantics for bitops IA64 are broken. Both > > smp_mb__after/before_clear_bit are now set to full memory barriers > > to compensate > > Why you say that? clear_bit has built-in acq or rel semantic depends > on how you define it. I think only one of smp_mb__after/before need to > be smp_mb? clear_bit has no barrier semantics just acquire. Therefore both smp_mb_* need to be barriers or they need to add some form of "release". > > +static __inline__ void > > +set_bit_mode (int nr, volatile void *addr, int mode) > > +{ > > + __u32 bit, old, new; > > + volatile __u32 *m; > > + CMPXCHG_BUGCHECK_DECL > > + > > + m = (volatile __u32 *) addr + (nr >> 5); > > + bit = 1 << (nr & 31); > > + > > + if (mode == MODE_NON_ATOMIC) { > > + *m |= bit; > > + return; > > + } > > Please kill all volatile declaration, because for non-atomic version, > you don't need to do any memory ordering, but compiler automatically > adds memory order because of volatile. It's safe to kill them because > cmpxchg later has explicit mode in there. Ok. V3 will have that. - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.htmlReceived on Fri Mar 31 11:42:54 2006
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