RE: accessed/dirty bit handler tuning

From: Chen, Kenneth W <kenneth.w.chen_at_intel.com>
Date: 2006-03-29 19:28:18
Zoltan Menyhart wrote on Wednesday, March 29, 2006 12:12 AM
> > The Itanium architects agree with you ... the architecture would allow
> > for an implementation where the itc becomes visible after the ld8 that
> > is checking the pte hasn't changed.
> > 
> > Ken and I messed with your patch a bit (to match the style of the rest
> > of ivt.S, and to drop some pointless differences between the trap 8, 9
> > and 10 handlers).  Here's what I plan to checkin:
> 
> Well, it looks correct.
> 
> We'll have to have a look at the other places like "vhpt_miss",...


Oh my gosh, my worst nightmare becomes the reality, :-( It is unacceptable
to have srlz.d in vhpt_miss.  Couple of alternatives:

(1) strip off all ptc.g related instructions in vhpt and just let the hpw
    walker do the job.  Kernel can take double faults, but after all, with
    what people do to ia64 kernel, this might be the best solution.

(2) add 20 cycles of delay in front of ptc.g

(3) dynamically patch out srlz.d for McK/Madison/Montecito processor.

(4) .....

- Ken
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Received on Wed Mar 29 19:28:09 2006

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