Ken, On Fri, Feb 10, 2006 at 12:33:20PM -0800, Chen, Kenneth W wrote: > Stephane Eranian wrote on Friday, February 10, 2006 5:35 AM > > Suposing I move up the PERFMON_VECTOR to 0xf1, it will be in the > > top priority class (15) with the following vectors: > > > > Today, the PMU interrupt handler runs with interrupts disabled, > > as such the situation would not be different. In fact, we could > > skip masking/unmasking because we would be in the top class + > > TPR masking done by the kernel on interrupt. > > > > Anybody, has a problem with this? > > If your goal is to be able to sample timer interrupt with PMU, you > won't get it even after you move PMU vector one class up. Because > just like PMU vector, timer interrupt handler is run with interrupt > off all the through. > Are you talking about timer_interrupt()? Where is the masking happening exactly? -- -Stephane - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.htmlReceived on Sat Feb 11 08:27:24 2006
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