RE: [patch 1/6] align kenrel rbs on 128 byte

From: Chen, Kenneth W <kenneth.w.chen_at_intel.com>
Date: 2006-02-01 03:25:37
Jes Sorensen wrote on Tuesday, January 31, 2006 3:01 AM
> Ken> Keith Owens wrote on Tuesday, January 31, 2006 12:57 AM
> >> The cache lines are not guaranteed to be 128 byte aligned, they
> >> were 64 on bigsur.  Change 127 to (L1_CACHE_BYTES - 1).
> 
> Ken> That did cross my mind and L1_CACHE_BYTES is such a misleading
> Ken> name.  In my head, L1 means the cache level closest to the CPU
> Ken> core, but here it appears to represent last level cache line.  Do
> Ken> we have the numbering scheme reversed?  I have no idea what's
> Ken> going on here.
> 
> Shouldn't this be SMP_CACHE_BYTES if anything?


Yeah, if nobody cares about UP performance. SMP_CACHE_BYTES is 8 bytes
on UP kernel (though it doesn't seem that anyone cares about UP).  I
will consult Tony to see what he likes.  I might settle with
L1_CACHE_BYTES.  I can just see people is going yell at me for having
125 column line :-p  :-))

- Ken

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Received on Wed Feb 01 03:26:23 2006

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