Re: [patch 1/6] align kenrel rbs on 128 byte

From: Jes Sorensen <jes_at_sgi.com>
Date: 2006-01-31 22:00:59
>>>>> "Ken" == Chen, Kenneth W <kenneth.w.chen@intel.com> writes:

Ken> Keith Owens wrote on Tuesday, January 31, 2006 12:57 AM
>> The cache lines are not guaranteed to be 128 byte aligned, they
>> were 64 on bigsur.  Change 127 to (L1_CACHE_BYTES - 1).

Ken> That did cross my mind and L1_CACHE_BYTES is such a misleading
Ken> name.  In my head, L1 means the cache level closest to the CPU
Ken> core, but here it appears to represent last level cache line.  Do
Ken> we have the numbering scheme reversed?  I have no idea what's
Ken> going on here.

Ken,

Shouldn't this be SMP_CACHE_BYTES if anything?

Cheers,
Jes
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Received on Tue Jan 31 22:01:34 2006

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