Re: [ia64-technical] Re: First Montecito Reference Manual is now available

From: Matthew Chapman <matthewc_at_cse.unsw.edu.au>
Date: 2006-01-19 01:11:47
On Thu, Jan 19, 2006 at 12:14:53AM +1100, Matthew Chapman wrote:
> 
> It seems to me that, at least at the L2TLB level, the "untagged" model
> could be implemented as an alternative at minimal cost;  e.g. OR the
> control bit into the tag.

Having thought it through, it may not be quite that simple, because of
RR prevalidation.  I'd guess that perhaps on Montecito the Active (RR
match) bit is set on both sets of entries to avoid revalidation on
thread switch?  And you sure don't want the set of mappings merged if
the two threads have different RRs!

In principle I still like the idea of an untagged mode, however...
especially since Itanium is targetted at HPC, and such workloads tend
to have overlap in working sets.  Just my 2c :)

Matt

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Received on Thu Jan 19 01:12:30 2006

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