RE: [RFC] 4-level page table directories.

From: Chen, Kenneth W <kenneth.w.chen_at_intel.com>
Date: 2005-11-09 07:07:02
Magenheimer, Dan wrote on Tuesday, November 08, 2005 10:53 AM
> The cost is of course a global (or cpu) variable access for
> every pud/pgd/pmd/pte macro usage, but one would expect the
> global would always be in cache/TLB so the performance impact
> should be near zero.

That is only true when your entire working set fits into the
cache (both kernel and user data).  Here you burn an extra cache
line for global page size variable, it will displace one cache
line for user application.  Enterprise workloads all have working
set much bigger than CPU's last level cache.  In the end, both
kernel and user side hurt with more cache miss rate.

- Ken

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Received on Wed Nov 09 07:07:50 2005

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