From: Hidetoshi Seto <seto.hidetoshi_at_jp.fujitsu.com>
Date: 2005-09-12 16:59:04
Hi all,

I'm now testing the MCA codes on brand-new system,
and bump into a problem that slave processors infinitely
loop in ia64_mca_wakeup_ipi_wait().

The cause was that the SAL clears the IRR bit just after its
spin in SAL_MC_RENDEZ procedure, and OS spins again until the
IRR bit be set in ia64_mca_wakeup_ipi_wait().

According to the SAL spec, it says:
   When this procedure returns, it is the responsibility of the
   operating system to clear the IRR bits for the MC_rendezvous
   interrupt and the wake up interrupt, if any.

I'm not sure but it seems "if any" means that SAL can clear
the IRR bits on behalf of OS.  So OS shouldn't expect the IRR
always be set on returning from SAL_MC_RENDEZ, is this right?

I found a archive 2 years ago, from Keith:
However there was no responce...

I don't know whether there is any old SAL never spins in
SAL_MC_RENDEZ or not.  Or is this the beginning of nightmare,
having different MCA codes depend on the SAL version?


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Received on Mon Sep 12 17:00:07 2005

This archive was generated by hypermail 2.1.8 : 2005-09-12 17:00:13 EST