RE: [patch] Memory Error Handling Improvement

From: Luck, Tony <tony.luck_at_intel.com>
Date: 2005-06-25 07:05:00
>will not help at all.  Furthermore, if MCA delivery timing changes for
>some reason, the user-triggered MCA might show up much later, i.e.,
>pretty much anywhere in the kernel no?

Not really.  Suppose there is some location in memory that has a multi-bit
ECC error, and the user reads this location:

	ld8 r17=[r18]

Now the MCA mechanism is asynchronous ... so nothing may happen right away,
but there is a guarantee that at the very latest the MCA will be delivered
before the poisoned data is consumed.  So suppose that we happen to try to
enter the kernel for some reason before the MCA is delivered.  Since the
kernel saves all the users registers, it will attempt to consume the data,
and so the MCA will be delivered.

For the user-mode MCA to survive to an arbitrary point in the kernel would
mean that we didn't save some user mode register.

-Tony
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Received on Fri Jun 24 17:14:52 2005

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:40 EST