Re: Simple Stupid Performance counters

From: David Mosberger <davidm_at_napali.hpl.hp.com>
Date: 2005-05-02 21:39:14
>>>>> On Fri, 29 Apr 2005 13:14:33 -0700 (PDT), Christoph Lameter <clameter@engr.sgi.com> said:

  Christoph> Time is measured using the cycle counter (TSC on IA32,
  Christoph> ITC on IA64) which has a very low latency.

Very low latency?  I guess that's relative, but at 36 cycles, AR.ITC
is one of the slowest registers.  If done properly, you can normally
hide the latency of the first read (assuming you don't have too many
other AR/CR accesses pending), but I see that your macros don't do
that either:

+#define PC_START(x) x=(get_cycles() << 8) + smp_processor_id()

The shift & add ensure that even PC_START() will incur the full 36
cycle latency.

	--david
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Received on Mon May 2 07:39:38 2005

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