[patch] fix syscall-optimization goof

From: David Mosberger <davidm_at_napali.hpl.hp.com>
Date: 2005-03-18 17:38:10
[Resend with list-addres corrected...]

Sadly, I goofed in this syscall-tuning patch:

ChangeSet 1.1966.1.40 2005/01/22 13:31:05 davidm@hpl.hp.com
  [IA64] Improve ia64_leave_syscall() for McKinley-type cores.

  Optimize ia64_leave_syscall() a bit better for McKinley-type cores.
  The patch looks big, but that's mostly due to renaming r16/r17 to r2/r3.
  Good for a 13 cycle improvement.

The problem is that the size of the physical stacked registers was
loaded into the wrong register (r3 instead of r17).  Since r17 by
coincidence always had the value 1, this had the effect of turning
rse_clear_invalid into a no-op.  That poses the risk of leaking kernel
state back to user-land and is hence not acceptable.

The fix below is simple, but unfortunately it costs us about 28 cycles
in syscall overhead. ;-(

Unfortunately, there isn't much we can do about that since those
registers have to be cleared one way or another.

	--david

===== arch/ia64/kernel/entry.S 1.80 vs edited =====
--- 1.80/arch/ia64/kernel/entry.S	2005-01-28 16:37:04 -08:00
+++ edited/arch/ia64/kernel/entry.S	2005-03-17 22:30:15 -08:00
@@ -759,8 +759,8 @@
 	ld8.fill r15=[r3]	// restore r15
 	addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0
 	;;
-(pUStk)	ld4 r3=[r3]		// r3 = cpu_data->phys_stacked_size_p8
 (pUStk) st1 [r14]=r17
+(pUStk)	ld4 r17=[r3]		// r17 = cpu_data->phys_stacked_size_p8
 	mov b6=r18		// I0  restore b6
 	;;
 	mov r14=r0		// clear r14
-
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Received on Fri Mar 18 01:38:28 2005

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:37 EST