[PATCH 2.6.11-rc3 0/0] Altix: Fix TIO DMA Macro to support both Shub1 and Shub2

From: Colin Ngam <cngam_at_sgi.com>
Date: 2005-03-05 04:02:37
This patch enables our TIO IO chipset to support variable length nasids in 
Shub2 chipset.

Signed-off-by: Colin Ngam <cngam@sgi.com>

===== include/asm-ia64/sn/addrs.h 1.11 vs edited =====
--- 1.11/include/asm-ia64/sn/addrs.h	2004-12-10 14:10:33 -06:00
+++ edited/include/asm-ia64/sn/addrs.h	2005-03-03 15:20:37 -06:00
@@ -153,8 +153,9 @@
  *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
  *           to insert a chiplet id into this macro.  However, it is our belief
  *           right now that this chiplet id will be ICE, which is also zero.
+ *           Nasid starts on bit 40.
  */
-#define PHYS_TO_TIODMA(x)	( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
+#define PHYS_TO_TIODMA(x)	( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
 #define PHYS_TO_DMA(x)          ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
 
 
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Received on Fri Mar 4 12:15:29 2005

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:36 EST