Re: Page fault scalability patch V18: Drop first acquisition of ptl

From: David S. Miller <>
Date: 2005-03-03 16:38:31
On Thu, 3 Mar 2005 16:00:10 +1100
Paul Mackerras <> wrote:

> Andrew Morton writes:
> > But if the approach which these patches take is not suitable for these
> > architectures then they have no solution to the scalability problem.  The
> > machines will perform suboptimally and more (perhaps conflicting)
> > development will be needed.
> We can do a pte_cmpxchg on ppc64.

We really can't make use of this on sparc64.  Unlike ppc64 I don't
have the hash table issue (although sparc64 TLB's have a hash lookup
helping mechanism in hardware, which we ignore since virtually mapped
linear page tables are faster than Sun's bogus TSB table scheme).

I make all real faults go through the handle_mm_fault() path so all
page table modifications are serialized by the page table lock.
The TLB miss handlers never modify PTEs, not even to update access
and dirty bits.

Actually, I guess I could do the pte_cmpxchg() stuff, but only if it's
used to "add" access.  If the TLB miss handler races, we just go into
the handle_mm_fault() path unnecessarily in order to synchronize.

However, if this pte_cmpxchg() thing is used for removing access, then
sparc64 can't use it.  In such a case a race in the TLB handler would
result in using an invalid PTE.  I could "spin" on some lock bit, but
there is no way I'm adding instructions to the carefully constructed
TLB miss handler assembler on sparc64 just for that :-)
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Received on Thu Mar 3 00:47:25 2005

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:36 EST