Re: [rfc] generic allocator and mspec driver

From: Grant Grundler <iod00d_at_hp.com>
Date: 2005-02-16 04:35:46
On Tue, Feb 15, 2005 at 03:43:10AM -0500, Jes Sorensen wrote:
> None of the ones I know well have this problem, but I have little
> knowledge about this level of stuff on most architectures. The ones
> that could have issues would probably be like PPC, PARISC and maybe
> Alpha .....

With parisc 2.0 CPU, one could map the same physical address
as both cacheable and uncacheable via two entries in the page table.
AFAIK, the uncacheable bit is only use to map MMIO address space.
In practice, I'm not sure what happens since I'm not aware of
any need for both mappings at the same time because we can use
"LDWA" (Load Word Absolute). LDWA can load from (almost) any physical
address and is by nature uncached (caches are VIVT).

Older PA1.x CPU had hardwired 0xf0000000-0xffffffff to be uncacheable.
I.e. it's not possible to have an overlap.

hth,
grant
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Received on Tue Feb 15 12:39:20 2005

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:35 EST