Re: page table lock patch V15 [0/7]: overview II

From: Andi Kleen <>
Date: 2005-01-14 22:11:21
On Fri, Jan 14, 2005 at 09:57:16PM +1100, Nick Piggin wrote:
> Andi Kleen wrote:
> >>I have a question for the x86 gurus. We're currently using the lock
> >>prefix for set_64bit. This will lock the bus for the RMW cycle, but
> >>is it a prerequisite for the atomic 64-bit store? Even on UP?
> >
> >
> >An atomic 64bit store doesn't need a lock prefix. A cmpxchg will
> >need to though.
> Are you sure the cmpxchg8b need a lock prefix? Sure it does to

If you want it to be atomic on SMP then yes.

> get the proper "atomic cmpxchg" semantics, but what about a
> simple 64-bit store... If it boils down to 8 byte load, 8 byte

A 64bit store with a 64bit store instruction is atomic. But 
to do that on 32bit x86 you need SSE/MMX (not an option in the kernel)
or cmpxchg8 

> store on the memory bus, and that store is atomic, then maybe
> a lock isn't needed at all?

More complex operations than store or load are not atomic without
LOCK (and not all operations can have a lock prefix). There are a few 
instructions with implicit lock. If you want the gory details read 
chapter 7 in the IA32 Software Developer's Manual Volume 3.


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Received on Fri Jan 14 06:11:41 2005

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