Re: page fault scalability patch final : i386 tested, x86_64 support added

From: Andi Kleen <>
Date: 2004-08-28 11:17:59
On Fri, Aug 27, 2004 at 06:11:42PM -0700, David S. Miller wrote:
> On 28 Aug 2004 03:05:42 +0200
> Andi Kleen <> wrote:
> > I would expect most programs to be not have that many holes,
> Holes are not the issue.

Holey parts will be quickly skipped in pml4.

> clear_page_tables() doesn't even use the VMA list as a guide
> (it actually can't), it just walks the page tables one pgd at a
> time, one pmd at a time, one pte at a time.  And this has the
> worst cache behavior even for simple cases like lat_proc
> in lmbench.
> Each pgd/pmd scan is a data reading walk of a whole page
> (or whatever size the particular page table level blocks
> are for the platform, usually they are PAGE_SIZE).
> It's very costly.

Ok, haven't done measurements yet. I would hope though that
on any arch that needs 4 levels reading another PAGE_SIZE worth 
of memory is not prohibitive.

That said any optimizations are welcome of course.


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Received on Fri Aug 27 21:18:17 2004

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