Hi, I came to know recently that the itanium based processors do not implement the inclusion principle wrt caches ? Is this information correct ? This was a bit surprising, as I had imagined that inclusion would'nt be maitained perhaps only after a certain L1 cache size. What are the trade-offs involved ? Would there be any s/w (kernel) visible effects of not implementing inclusion ? thx, santosh. - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.htmlReceived on Fri Apr 30 07:44:31 2004
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