RE: cacheble to uncachble change

From: Smarduch Mario-CMS063 <>
Date: 2004-04-29 23:39:51
David, thanks for answering my implicit question.

- Mario

-----Original Message-----
From: David Mosberger [] 
Sent: Wednesday, April 28, 2004 11:50 PM
To: Smarduch Mario-CMS063
Cc: Robin Holt; Smarduch Mario-CMS063;; Jack Steiner; IA-64 Mailing List (New)
Subject: Re: cacheble to uncachble change

>>>>> On Wed, 28 Apr 2004 10:52:58 -0500, Mario Smarduch 
>>>>> <> said:

  Mario> But now that I look at it, it seems that TRs pin the kernel
  Mario> as well with cacheble attribute.

Yes, there are the pinned entries and, additionally, any address that's accessed via region 7 (address 0xe000...) will get mapped by the alternate TLB miss-handler with a granule-sized TLB entry.  The size of a granule is given by IA64_GRANULE_SIZE and is normally 64MB (but may be 16MB for machines that require it).

So if you map _anything_ uncachable, you need to reserve the _entire_
(naturally-aligned) granule (all 64/16MB of it) and then you'll be OK.

To unsubscribe from this list: send the line "unsubscribe linux-ia64" in
the body of a message to
More majordomo info at
Received on Thu Apr 29 09:41:31 2004

This archive was generated by hypermail 2.1.8 : 2005-08-02 09:20:25 EST