RE: cacheble to uncachble change

From: Smarduch Mario-CMS063 <CMS063_at_motorola.com>
Date: 2004-04-29 23:39:51
David, thanks for answering my implicit question.

- Mario

-----Original Message-----
From: David Mosberger [mailto:davidm@napali.hpl.hp.com] 
Sent: Wednesday, April 28, 2004 11:50 PM
To: Smarduch Mario-CMS063
Cc: Robin Holt; Smarduch Mario-CMS063; davidm@hpl.hp.com; Jack Steiner; IA-64 Mailing List (New)
Subject: Re: cacheble to uncachble change


>>>>> On Wed, 28 Apr 2004 10:52:58 -0500, Mario Smarduch 
>>>>> <cms063@email.mot.com> said:

  Mario> But now that I look at it, it seems that TRs pin the kernel
  Mario> as well with cacheble attribute.

Yes, there are the pinned entries and, additionally, any address that's accessed via region 7 (address 0xe000...) will get mapped by the alternate TLB miss-handler with a granule-sized TLB entry.  The size of a granule is given by IA64_GRANULE_SIZE and is normally 64MB (but may be 16MB for machines that require it).

So if you map _anything_ uncachable, you need to reserve the _entire_
(naturally-aligned) granule (all 64/16MB of it) and then you'll be OK.

	--david
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Received on Thu Apr 29 09:41:31 2004

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