RE: cacheble to uncachble change

From: Luck, Tony <tony.luck_at_intel.com>
Date: 2004-04-28 09:53:40
>  Mario> I guess the question wasn't so much about attribute aliasing
>  Mario> but killing all intransit memory accesses and prefetch before
>  Mario> its safe to change the TLB attribute to uncacheble, with
>  Mario> assurance that all new mem refs/prefetch will come from
>  Mario> memory. I appreciate all your inputs.
>
>  David>Yes, but that's the _easy_ part, so to speak.

Buried in one of the e-mails on this thread was the fact that you must
allocate a whole granule (16MB or 64MB ... check your .config) to make
sure that you don't have a kernel cacheable mapping setup by the
Alt-DTLB
miss handler.

-Tony
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Received on Tue Apr 27 19:56:30 2004

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