latencies for uncommon instructions on I2

From: Matt Chapman <matthewc_at_cse.unsw.edu.au>
Date: 2004-03-27 11:50:58
Has anyone collated best case latency information for I2 similar to the tables
in the last chapter of the I1 architecture manual?  The I2 architecture manual
is somewhat more vague and doesn't quote latencies for many instructions.

I'm especially interested in latencies for:

- read and write to ar.k*
- flushrs with no dirty registers, loadrs 0, invala
- epc

Matt

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Received on Fri Mar 26 19:51:23 2004

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