Re: Excessive time to handle interrupts

From: David Mosberger <davidm_at_napali.hpl.hp.com>
Date: 2004-02-27 11:06:07
>>>>> On Fri, 27 Feb 2004 10:44:25 +1100, Peter Chubb <peter@chubb.wattle.id.au> said:

  Peter> writel(IOSAPIC_RTE_LOW(rte_index), addr + IOSAPIC_REG_SELECT);
  Peter> low32 = readl(addr + IOSAPIC_WINDOW);
  Peter> low32 &= ~(1 << IOSAPIC_MASK_SHIFT);    /* set only the mask bit */
  Peter> writel(low32, addr + IOSAPIC_WINDOW);

  Peter> I don't know enough about the hardware to say for sure

See:

  http://www.intel.com/design/itanium/downloads/25135001.pdf

  Peter> is it feasible to keep a soft copy of the register rather
  Peter> than do the read all the time?  If that's not going to break
  Peter> the hardware, I'll code it up and see if interrupt latencies
  Peter> go down.

AFAIR, the I/O SAPIC interrupt masking is entirely under control of
the CPU (i.e., the hw never changes the mask of its own) so caching
sounds like a good idea.

FYI: I'm planning to do a q-syscollect enhancement which would let you
get at least a flat profile for code which disables interrupts (or
even interrupt collection).

	--david
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Received on Thu Feb 26 19:16:40 2004

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