pal/power_info for real?

From: Duraid Madina <duraid_at_octopus.com.au>
Date: 2003-11-25 20:09:31
Hi all,

	/proc/pal/cpu0/power_info on my system reads:

Power level 0:
         entry_latency       : 9000 cycles
         exit_latency        : 8700 cycles
         power consumption   : 52000 mW
         Cache+TLB coherency : Yes
Power level 1: not implemented
Power level 2:
         entry_latency       : 14000 cycles
         exit_latency        : 8700 cycles
         power consumption   : 52000 mW
         Cache+TLB coherency : Yes
Power level 3: not implemented
Power level 4: not implemented
Power level 5: not implemented
Power level 6: not implemented
Power level 7: not implemented


	Is this correct? Two power levels, with different entry latencies, but 
the same power consumption?

	Bracing myself for a particularly warm summer,

	Duraid

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Received on Tue Nov 25 04:11:15 2003

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