On Wed, Nov 05, 2003 at 09:14:08AM -0800, Alberto Munoz wrote: > What implementation of the Itanium processor supports avoiding MCAs from > lfetch or code fetch operations? I don't think Itanium 1 or 2 do this. How > about Madison? Oops, misunderstanding here. Madison and Deerfield are also Itanium 2. It's like Coppermine and Tualatin are both Pentium 3. When the difference is only cache size, die size, clock frequency and so on, they're not going to change the number. For bigger changes, they might ;-) -- "It's not Hollywood. War is real, war is primarily not about defeat or victory, it is about death. I've seen thousands and thousands of dead bodies. Do you think I want to have an academic debate on this subject?" -- Robert Fisk - To unsubscribe from this list: send the line "unsubscribe linux-ia64" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.htmlReceived on Wed Nov 5 12:35:33 2003
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