Re: load-store emulation with SIGSEGV (gate.S bug?)

From: Keith Owens <kaos_at_ocs.com.au>
Date: 2003-10-18 01:34:20
On 17 Oct 2003 15:26:13 -0000, 
Jeffrey William Lake <lakes@lakes.plus.com> wrote:
>After some investigation I discovered that a "flushrs" at the start of my
>signal handler cured the problem.
>
>Looking at "arch/ia64/kernel/gate.S" revealed that a "cover" is used to
>get the registers onto the backing store (commented as such several
>times), but by my understanding there is enough scope from the instruction
>description that they may be cached.

cover only marks the current frame (r32+) as dirty.  It does not write
the dirty registers out to backing store, that is left to RSE to do at
its leisure.  flushrs forces RSE to write the dirty registers out to
memory.

>Therefore, should gate.S include a
>"flushrs" as well or, for performance reasons be left for the user to
>decide?

Probably best left for the user to decide.  The majority of signal
handlers will not require the registers to be flushed.

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Received on Fri Oct 17 11:53:18 2003

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