Re: load-store emulation with SIGSEGV

From: David Mosberger <davidm_at_napali.hpl.hp.com>
Date: 2003-10-17 09:57:53
>>>>> On Thu, 16 Oct 2003 23:49:20 +0100, "R. Lake" <rich@lakes.plus.com> said:

  Rich> I'm investigating a means of emulating causes of SEGV where
  Rich> they can be isolated from genuine failure. For example, a rule
  Rich> stating a load from address 0x100 "loads" the value 42 into
  Rich> the target register.

  Rich> A simple test to decode the instruction, locate and modify the
  Rich> operand register in the sigcontext or backing store, then
  Rich> increment sc_ip shows the expected behaviour. But, for
  Rich> practical usage I'm not entirely confident I've taken all the
  Rich> necessary steps to return to the kernel in a robust manner.
  Rich> I've thus far taken insight from the unaligned handler albeit
  Rich> without altering the psr.ri field. So, my question is... am I
  Rich> missing a vital stage to this process, some piece of
  Rich> information the kernel expects to receive when avoiding the
  Rich> faulting instruction?

I'm not entirely sure I understand what you're trying to do and
whether you're doing it in the kernel or user (signal-handler).  If
the latter, adjusting the sc_ip should be sufficient (the slot number
is encoded in bits 0 and 1 of sc_ip).

	--david
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Received on Thu Oct 16 19:58:11 2003

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