[PATCH 2.4] TLB error recovery (take 2)

Thanks for all the excellent feedback on the first iteration
of this patch (posted May 28) to enable recovery from MCA due
to TLB errors.

Here is a new version changed to address those issues.

Changes since last time:

1) Biggest change is to recode the routine that does the actual
purge and reload of the TR registers in assembler to avoid issues
with compilers (or compiler switches) generating code that will
not run in physical mode.  [Thanks Keith for pointing this out]

2) As a result of change '1' the data structure in which we save
the information needed for the reload has been pared down to just
include data for the IA64_TR_PALCODE and IA64_TR_PERCPU_DATA
registers, since the others are either hard-coded or derived from
kernel registers.  This array is indexed by Linux logical cpu number
when we initialize entries, but we also save "cr.lid" for each
processor so that the physical mode code can find the right entry
[If someone can show me a simple way to come up with the linux
logical cpu number from physical mode code, then we can simplify
this a lot]

3) The previous patch unconditionally purged and reloaded the TLB, this
one checks the 'tr' bit of the processor state parameter (passed by PAL
to SAL and on to the OS) to determine whether a fix is needed.

4) The previous version unconditionally set a return status of
IA64_MCA_CORRECTED. This version still sets IA64_MCA_COLD_BOOT
if there are any other errors.

5) I split out the code to restrict the register printout to just the
implemented registers into a separate patch (as all the print code
should be removed from the kernel ... and this patch applied to Bjorn's
"salinfo" utility).

-Tony

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